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1.发明公开公开(公告)号：US20240038667A1
公开(公告)日：2024-02-01
申请号：US17873476
申请日：2022-07-26
发明人： Ryo Nakamura , Naohiro Hosoda
IPC分类号： H01L23/535 , H01L27/11556 , H01L27/11582
CPC分类号： H01L23/535 , H01L27/11556 , H01L27/11582
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a composite insulating cap layer located over the alternating stack, memory openings vertically extending through the composite insulating cap layer and the alternating stack, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements. The composite insulating layer includes a bottom insulating cap layer, a top insulating cap layer, and an etch-stop dielectric layer located between the bottom insulating cap layer and the top insulating cap layer.
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公开(公告)号：US11417621B2
公开(公告)日：2022-08-16
申请号：US17113293
申请日：2020-12-07
IPC分类号： H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00 , H01L23/522 , H01L27/11582 , H01L27/11556
摘要： A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.
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公开(公告)号：US11367733B1
公开(公告)日：2022-06-21
申请号：US17113254
申请日：2020-12-07
发明人： Naohiro Hosoda , Masanori Tsutsumi , Kota Funayama
IPC分类号： H01L27/11556 , H01L27/11582 , H01L23/522 , H01L27/11526 , H01L27/11565 , H01L27/11573 , H01L27/11519
摘要： A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.
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4.发明授权公开(公告)号：US11289416B2
公开(公告)日：2022-03-29
申请号：US16695775
申请日：2019-11-26
发明人： Masanori Tsutsumi , Naohiro Hosoda , Shuichi Hamaguchi , Kazuki Isozumi , Genta Mizuno , Yusuke Mukae , Ryo Nakamura , Yu Ueda
IPC分类号： H01L29/76 , H01L23/522 , H01L23/532 , H01L27/11519 , H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11524
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
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公开(公告)号：US11011506B2
公开(公告)日：2021-05-18
申请号：US16847857
申请日：2020-04-14
发明人： Naohiro Hosoda , Kazuma Shimamoto , Tetsuya Shirasu , Yuji Fukano , Akio Nishida
IPC分类号： H01L25/18 , H01L27/11582 , G11C16/24 , G11C16/08 , G11C16/26 , H01L27/11519 , H01L27/11573 , H01L27/11556 , H01L27/11529 , H01L27/11565 , H01L27/1157 , H01L27/11524
摘要： A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
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6.发明授权公开(公告)号：US10903237B1
公开(公告)日：2021-01-26
申请号：US16671561
申请日：2019-11-01
发明人： Naohiro Hosoda , Hiroyuki Ogawa , Yuki Mizutani
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11524 , H01L23/528 , H01L27/1157 , H01L27/11565 , H01L23/522 , H01L27/11519
摘要： Memory stack structures and dielectric wall structures are formed through a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers. Backside trenches are formed to divide the vertically alternating sequence into multiple alternating stacks. First portions of the continuous sacrificial material layers are replaced with electrically conductive layers. A connection region including a pair of dielectric wall structures is provided between a first memory array region and a second memory array region of a first alternating stack. Second portions of the continuous sacrificial material layers remain between the pair of dielectric wall structures as a vertical stack of dielectric plates. An upper subset of the first electrically conductive layers is patterned and is divided into multiple discrete portions. The multiple discrete portions are electrically connected by a respective set of connection metal interconnect structures. A metal via structure may be formed through the dielectric plates.
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7.发明授权公开(公告)号：US10453798B2
公开(公告)日：2019-10-22
申请号：US15717102
申请日：2017-09-27
发明人： Masanori Tsutsumi , Naohiro Hosoda
IPC分类号： H01L23/535 , H01L21/768 , H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.
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8.发明授权公开(公告)号：US11894298B2
公开(公告)日：2024-02-06
申请号：US17655827
申请日：2022-03-22
发明人： Masanori Tsutsumi , Naohiro Hosoda , Shuichi Hamaguchi , Kazuki Isozumi , Genta Mizuno , Yusuke Mukae , Ryo Nakamura , Yu Ueda
IPC分类号： H01L23/522 , H01L23/532 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H01L23/5226 , H01L23/53223 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
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公开(公告)号：US10665580B1
公开(公告)日：2020-05-26
申请号：US16242216
申请日：2019-01-08
发明人： Naohiro Hosoda , Kazuma Shimamoto , Tetsuya Shirasu , Yuji Fukano , Akio Nishida
IPC分类号： H01L25/18 , H01L27/11582 , G11C16/24 , G11C16/08 , G11C16/26 , H01L27/11519 , H01L27/11573 , H01L27/11556 , H01L27/11529 , H01L27/11565 , H01L27/1157 , H01L27/11524
摘要： A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
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公开(公告)号：US10347647B1
公开(公告)日：2019-07-09
申请号：US15850073
申请日：2017-12-21
IPC分类号： H01L27/115 , H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L27/11582 , H01L27/1157 , H01L21/265 , H01L21/266 , H01L27/11524 , H01L29/40
摘要： A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
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