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公开(公告)号：US20170287926A1
公开(公告)日：2017-10-05
申请号：US15186768
申请日：2016-06-20
发明人： Junichi Ariyoshi
IPC分类号： H01L27/115 , H01L29/66 , H01L21/265 , H01L29/167 , H01L29/417
CPC分类号： H01L27/11582 , H01L21/26513 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/167 , H01L29/41741 , H01L29/6656
摘要： Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first insulating layers and first sacrificial material layers. Dopant species that retard or prevent etching of the material of the support opening fill structures can be implanted into an upper portion of each support opening fill structure, while memory-opening semiconductor material portions are masked from implantation. After formation of a second alternating stack and second openings therethrough, the sacrificial material of the memory-opening semiconductor material portions is removed while the support opening fill structures is not removed. Damage to the first sacrificial material layers during formation of the staircase contact region and resulting leakage paths from word lines to the substrate through support pillar structures can be avoided or reduced by not removing the support opening fill structures.
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公开(公告)号：US09786681B1
公开(公告)日：2017-10-10
申请号：US15186768
申请日：2016-06-20
发明人： Junichi Ariyoshi
IPC分类号： H01L29/167 , H01L27/11582 , H01L27/11556 , H01L29/417 , H01L21/265 , H01L29/66
CPC分类号： H01L27/11582 , H01L21/26513 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/167 , H01L29/41741 , H01L29/6656
摘要： Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first insulating layers and first sacrificial material layers. Dopant species that retard or prevent etching of the material of the support opening fill structures can be implanted into an upper portion of each support opening fill structure, while memory-opening semiconductor material portions are masked from implantation. After formation of a second alternating stack and second openings therethrough, the sacrificial material of the memory-opening semiconductor material portions is removed while the support opening fill structures is not removed. Damage to the first sacrificial material layers during formation of the staircase contact region and resulting leakage paths from word lines to the substrate through support pillar structures can be avoided or reduced by not removing the support opening fill structures.
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3.发明授权公开(公告)号：US10115681B1
公开(公告)日：2018-10-30
申请号：US15928337
申请日：2018-03-22
发明人： Junichi Ariyoshi
IPC分类号： H01L23/00 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/1157 , H01L21/768 , H01L27/11573 , H01L23/528 , H01L23/522 , H01L23/58 , H01L27/11582
摘要： A semiconductor die includes a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate, groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, such that each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers, and at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.
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公开(公告)号：US10381450B1
公开(公告)日：2019-08-13
申请号：US15906109
申请日：2018-02-27
发明人： Shinsuke Yada , Xiaolong Hu , Junichi Ariyoshi
IPC分类号： H01L29/423 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/11519 , H01L21/28 , H01L27/11582 , H01L27/11573 , H01L27/11565 , H01L27/1157
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.
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5.发明授权公开(公告)号：US10242994B2
公开(公告)日：2019-03-26
申请号：US15704370
申请日：2017-09-14
IPC分类号： H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11565 , H01L27/11519 , H01L29/792 , H01L27/11575
摘要： A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.
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公开(公告)号：US10347647B1
公开(公告)日：2019-07-09
申请号：US15850073
申请日：2017-12-21
IPC分类号： H01L27/115 , H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L27/11582 , H01L27/1157 , H01L21/265 , H01L21/266 , H01L27/11524 , H01L29/40
摘要： A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
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公开(公告)号：US10256245B2
公开(公告)日：2019-04-09
申请号：US15632703
申请日：2017-06-26
发明人： Junichi Ariyoshi
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L23/522 , H01L27/11565 , H01L27/11582 , H01L27/11573
摘要： Electrical short caused by misalignment of source select level contact via structure and support pillar structures can be prevented by modifying the pattern of the support pillar structures such that the support pillar structures are omitted from the area in which source select gate contact via structures are formed. The insulating layer at the level overlying the source select level electrically conductive layer can have a sufficient thickness to prevent deformation during formation of the backside recesses. A minimum lateral separation distance between the source select level contact via structure and the support pillar structures is greater than any minimum lateral separation distance between the word line level contact via structures and the support pillar structures.
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公开(公告)号：US10083982B2
公开(公告)日：2018-09-25
申请号：US15496359
申请日：2017-04-25
发明人： Keisuke Shigemura , Junichi Ariyoshi , Masanori Tsutsumi , Michiaki Sano , Yanli Zhang , Raghuveer S. Makala
IPC分类号： H01L27/115 , H01L21/28 , H01L21/768 , H01L27/11582 , H01L27/11556 , H01L29/423 , H01L23/528 , H01L23/532 , H01L27/11524 , H01L21/311 , H01L27/1157 , H01L27/11526 , H01L27/11573 , H01L27/11519 , H01L27/11565 , H01L21/3213
CPC分类号： H01L27/11582 , H01L21/28008 , H01L21/31111 , H01L21/76843 , H01L21/76877 , H01L23/528 , H01L23/53266 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/42324 , H01L29/4234
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
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9.发明申请公开(公告)号：US20180261613A1
公开(公告)日：2018-09-13
申请号：US15632703
申请日：2017-06-26
发明人： Junichi Ariyoshi
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/11582 , H01L27/1157 , H01L23/522
CPC分类号： H01L27/11556 , H01L23/5226 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： Electrical short caused by misalignment of source select level contact via structure and support pillar structures can be prevented by modifying the pattern of the support pillar structures such that the support pillar structures are omitted from the area in which source select gate contact via structures are formed. The insulating layer at the level overlying the source select level electrically conductive layer can have a sufficient thickness to prevent deformation during formation of the backside recesses. A minimum lateral separation distance between the source select level contact via structure and the support pillar structures is greater than any minimum lateral separation distance between the word line level contact via structures and the support pillar structures.
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