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公开(公告)号：US20190066781A1
公开(公告)日：2019-02-28
申请号：US15691801
申请日：2017-08-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bijesh Rajamohanan , Srinitya Musunuru , Emmanuelle Merced-Grafals
IPC: G11C13/00
Abstract: A memory device is provided that includes a memory array having a plurality of reversible resistance-switching memory cells, and a memory controller coupled to the memory array. The memory controller is adapted to program a first reversible resistance-switching memory cell in the memory array to a predetermined data state, determine a program loop count associated with the program step, and retire the first reversible resistance-switching memory cell from further use for host data storage based on the associated program loop count.
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