公开(公告)号：US20190088323A1

公开(公告)日：2019-03-21

申请号：US15706562

申请日：2017-09-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Emmanuelle Merced-Grafals ,  Juan P. Saenz

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/00 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146

Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.

公开(公告)号：US10354724B2

公开(公告)日：2019-07-16

申请号：US15706562

申请日：2017-09-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Emmanuelle Merced-Grafals ,  Juan P. Saenz

IPC: G11C11/00 ,  G11C13/00

Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.

公开(公告)号：US20190066781A1

公开(公告)日：2019-02-28

申请号：US15691801

申请日：2017-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bijesh Rajamohanan ,  Srinitya Musunuru ,  Emmanuelle Merced-Grafals

IPC: G11C13/00

Abstract: A memory device is provided that includes a memory array having a plurality of reversible resistance-switching memory cells, and a memory controller coupled to the memory array. The memory controller is adapted to program a first reversible resistance-switching memory cell in the memory array to a predetermined data state, determine a program loop count associated with the program step, and retire the first reversible resistance-switching memory cell from further use for host data storage based on the associated program loop count.

公开(公告)号：US20180277208A1

公开(公告)日：2018-09-27

申请号：US15714463

申请日：2017-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepak Kamalanathan ,  Juan P. Saenz ,  Tanmay Kumar ,  Emmanuelle Merced-Grafals ,  Sebastian J. M. Wicklein

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/5664 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2213/54 ,  G11C2213/71 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: A memory device is provided that includes a memory controller coupled to a memory cell including a barrier modulated switching structure. The memory controller is adapted to program the memory cell to a first programming state, and program the memory cell to one of a plurality of target programming states from the first programming state.