公开(公告)号：US09397026B2

公开(公告)日：2016-07-19

申请号：US14172247

申请日：2014-02-04

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Tomoyuki Yoshino

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device comprises a semiconductor chip mounted on an island, and a plurality of leads spaced form the island and connected by wires to the semiconductor chip. An insulating film encapsulates the island, the semiconductor chip, the wires and the leads, and the insulating resin has a concave portion that is in contact with the leads. Each lead has a bottom surface exposed from the insulating resin, and the concave portion of the insulating resin exposes side surfaces which surround the bottom surface of each of the leads located under a bottom surface of the insulating resin. When the semiconductor device is soldered to a circuit board, the concave portion prevents contact between the solder and the insulating resin and improves self-alignment of the semiconductor device on the circuit board.

Abstract translation: 一种半导体器件包括安装在岛上的半导体芯片以及与该岛隔开的多个引线，并通过导线连接到该半导体芯片。 绝缘膜封装岛，半导体芯片，电线和引线，并且绝缘树脂具有与引线接触的凹部。 每个引线具有从绝缘树脂露出的底表面，并且绝缘树脂的凹部露出包围位于绝缘树脂的底表面下方的每个引线的底表面的侧表面。 当半导体器件被焊接到电路板时，凹部防止焊料和绝缘树脂之间的接触，并改善电路板上的半导体器件的自对准。

公开(公告)号：US09385057B2

公开(公告)日：2016-07-05

申请号：US14485927

申请日：2014-09-15

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Tomoyuki Yoshino

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/28 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00011

Abstract: A semiconductor flat package has a semiconductor chip, leads connected to the semiconductor chip, and an encapsulation resin covering the semiconductor chip and partially covering the leads. Outer end surfaces of the leads are exposed from the encapsulation resin and covered with a plated layer, and a side end surface of the plated layer and a side end surface of the encapsulation resin are flush with each other. A material with good solder wettability is formed at a lead cut portion of the semiconductor flat package, to thereby improve solder connection strength with a circuit board. A solder fillet is formed from the lead cut portion of the semiconductor package, to thereby enable adaptation of solder automatic visual inspection after mounting.

Abstract translation: 半导体平面封装具有半导体芯片，连接到半导体芯片的引线以及覆盖半导体芯片并部分地覆盖引线的封装树脂。 引线的外端面从密封树脂露出并被镀层覆盖，镀层的侧端面和封装树脂的侧端面相互齐平。 在半导体平面封装的引线切割部分处形成具有良好焊料润湿性的材料，从而提高与电路板的焊接连接强度。 由半导体封装的引线切割部形成焊锡圆角，从而能够在安装后适应焊料自动目视检查。