STRAY INDUCTANCE REDUCTION IN PACKAGED SEMICONDUCTOR DEVICES

    公开(公告)号:US20210066256A1

    公开(公告)日:2021-03-04

    申请号:US16671450

    申请日:2019-11-01

    Abstract: In a general aspect, a semiconductor device can include a substrate and a positive power supply terminal electrically coupled with the substrate, the positive power supply terminal being arranged in a first plane. The device can also include a first negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The device can further include a second negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The positive power supply terminal can be disposed between the first and second negative power supply terminals. The device can also include a conductive clip electrically coupling the first negative power supply terminal with the second negative power supply terminal via a conductive bridge. A portion of the conductive bridge can be arranged in a second plane that is parallel to, and non-coplanar with the first plane.

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