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公开(公告)号：US20240274568A1
公开(公告)日：2024-08-15
申请号：US18496612
申请日：2023-10-27
发明人： Edgardo LABER , James Edwin VINSON
CPC分类号： H01L24/48 , H01L23/62 , H01L24/45 , H02J7/0029 , H01L23/498 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247
摘要： A package for use with an integrated circuit having a contact pad is provided. The package includes an enclosure portion; a package pin for external connection; and a protective element coupled between the contact pad and the package pin. The protective element is operable in a first state or a second state. In the first state the protective element passes a current between the contact pad and the package pin. When the current is above a threshold value the protective element changes from the first state to the second state to prevent the current from flowing between the contact pad and the package pin.
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公开(公告)号：US20240203847A1
公开(公告)日：2024-06-20
申请号：US18084143
申请日：2022-12-19
发明人： Dae Young Park , Gi Jeong Kim , Hyeong Il Jeon , Kwang Soo Sang
IPC分类号： H01L23/498 , H01L21/48 , H01L21/56 , H01L23/31
CPC分类号： H01L23/498 , H01L21/485 , H01L21/56 , H01L23/3178
摘要： In one example, an electronic device comprises a substrate comprising a first side and a second side opposite the first side, wherein the substrate comprises a first groove at the second side of the substrate, a first electronic component over the first side of the substrate, and a resin in the first groove. The substrate comprises a floating pad at the first side of the substrate, a second groove at the first side of the substrate, and a third groove at the first side of the substrate, wherein the floating pad is between the second groove and the third groove. Other examples and related methods are also disclosed herein.
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公开(公告)号：US11942389B2
公开(公告)日：2024-03-26
申请号：US17330787
申请日：2021-05-26
申请人： Qorvo US, Inc.
发明人： Julio C. Costa , George Maxim
IPC分类号： H01L23/28 , H01L23/31 , H01L23/36 , H01L23/482 , H01L23/495 , H01L23/498 , H05K1/02
CPC分类号： H01L23/36 , H01L23/3128 , H01L23/4828 , H01L23/49568 , H01L23/498 , H05K1/021 , H05K2201/09118
摘要： The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
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公开(公告)号：US20240088046A1
公开(公告)日：2024-03-14
申请号：US18515657
申请日：2023-11-21
IPC分类号： H01L23/535 , G06F30/394 , H01L21/48 , H01L21/768 , H01L23/498 , H01L27/02 , H01L27/118
CPC分类号： H01L23/535 , G06F30/394 , H01L21/4846 , H01L21/486 , H01L21/76895 , H01L23/498 , H01L23/49827 , H01L27/0207 , H01L27/11807 , H01L2027/11875
摘要： A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.
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公开(公告)号：US11923279B2
公开(公告)日：2024-03-05
申请号：US18076861
申请日：2022-12-07
发明人： Nobutoshi Fujii , Yoshihisa Kagawa
IPC分类号： H01L23/498 , H01L23/00 , H01L23/522 , H01L23/532 , H01L25/00 , H01L25/065 , H01L27/146
CPC分类号： H01L23/498 , H01L23/49866 , H01L23/522 , H01L23/53238 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L25/0657 , H01L25/50 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L24/80 , H01L2224/05547 , H01L2224/05571 , H01L2224/0603 , H01L2224/06131 , H01L2224/06133 , H01L2224/0616 , H01L2224/06517 , H01L2224/08123 , H01L2224/08147 , H01L2224/09517 , H01L2224/80194 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06565 , H01L2924/00012 , H01L2924/00014 , H01L2924/01029 , H01L2924/12043 , H01L2924/13091 , H01L2224/05571 , H01L2924/00012 , H01L2924/00014 , H01L2224/05552 , H01L2924/13091 , H01L2924/00 , H01L2924/12043 , H01L2924/00
摘要： A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction.
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公开(公告)号：US11862571B2
公开(公告)日：2024-01-02
申请号：US17693545
申请日：2022-03-14
发明人： Byoung-Gug Min , Younhee Kang , Min-Woo Song
IPC分类号： H01L23/552 , H01L23/498 , H01L25/00
CPC分类号： H01L23/552 , H01L23/498 , H01L25/00
摘要： A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.
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公开(公告)号：US11862568B2
公开(公告)日：2024-01-02
申请号：US17734156
申请日：2022-05-02
IPC分类号： H01L23/535 , H01L27/118 , G06F30/394 , H01L21/48 , H01L21/768 , H01L23/498 , H01L27/02
CPC分类号： H01L23/535 , G06F30/394 , H01L21/486 , H01L21/4846 , H01L21/76895 , H01L23/498 , H01L23/49827 , H01L27/0207 , H01L27/11807 , H01L2027/11875
摘要： A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.
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8.发明授权公开(公告)号：US11842997B2
公开(公告)日：2023-12-12
申请号：US17699680
申请日：2022-03-21
申请人： Wolfspeed, Inc.
发明人： Terry Alcorn , Daniel Namishia , Fabian Radulescu
IPC分类号： H01L27/06 , H01L21/683 , H01L21/768 , H01L21/8258 , H01L23/48 , H01L23/498 , H01L23/00
CPC分类号： H01L27/0694 , H01L21/6835 , H01L21/76898 , H01L21/8258 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/16 , H01L24/73 , H01L27/0605 , H01L2224/1357 , H01L2224/13147 , H01L2224/16225 , H01L2224/73257 , H01L2924/1421
摘要： An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.
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公开(公告)号：US20230391611A1
公开(公告)日：2023-12-07
申请号：US18206520
申请日：2023-06-06
申请人： SiTime Corporation
发明人： Pavan Gupta , Aaron Partridge , Markus Lutz
IPC分类号： B81B7/00 , B81C1/00 , H10N30/30 , H01L23/34 , H01L23/498
CPC分类号： B81B7/0083 , B81C1/0023 , H10N30/302 , H01L23/34 , H01L23/498 , B81B7/007 , B81C1/00301 , B81B7/0077 , B81C1/00333 , B81C1/00341 , H01L2924/181 , H01L2224/48247 , H01L2924/01019 , H01L2224/48091 , H01L2224/73265 , H01L2924/1461 , B81B2201/0271 , B81C2203/0154 , H01L23/3107
摘要： A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.
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公开(公告)号：US20230254566A1
公开(公告)日：2023-08-10
申请号：US18304983
申请日：2023-04-21
申请人： LG INNOTEK CO., LTD.
发明人： Jae Keun PARK
IPC分类号： H04N23/57 , G02B7/00 , H01L27/146 , G02B13/00 , G02B7/08 , H04N23/54 , H04N23/55 , G02B7/09 , G02B27/64 , G03B5/00 , G03B11/00 , G03B13/36 , H01L23/498 , H05K1/14
CPC分类号： H04N23/57 , G02B7/004 , H01L27/14625 , H01L27/14618 , G02B13/001 , G02B7/08 , H04N23/54 , H04N23/55 , G02B7/09 , G02B27/646 , G03B5/00 , G03B11/00 , G03B13/36 , H01L23/498 , H01L27/14636 , H05K1/144 , H05K1/147 , G02B7/021
摘要： A camera module includes a lens driving device having a housing, a first circuit board disposed below the housing, a filter disposed on an upper surface of the first circuit board, a second circuit board disposed below the first circuit board, an image sensor disposed on the second circuit board and coupled to a lower surface of the first circuit board, and a first adhesive member disposed between the lower surface of the first circuit board and an upper surface of the second circuit board, and electrically connecting the first circuit board and the second circuit board. A lower surface of the image sensor is higher than the upper surface of the second circuit board.
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