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公开(公告)号：US20240215359A1
公开(公告)日：2024-06-27
申请号：US18554148
申请日：2022-03-20
IPC分类号： H10K59/131 , H10K59/12 , H10K59/121 , H10K59/35 , H10K71/00
CPC分类号： H10K59/131 , H10K59/1201 , H10K59/1213 , H10K59/352 , H10K59/353 , H10K71/00
摘要： A display device with high display quality is provided. A highly reliable display device is provided. A display device with low power consumption is provided. A display device that can easily achieve higher definition is provided. A display device with both high display quality and high definition is provided. A display device with high contrast is provided. The display device includes a first wiring to a fourth wiring and a display portion including a first pixel to a third pixel. The second pixel is positioned between the first pixel and the third pixel in a plan view. Each pixel includes a first subpixel and a second subpixel. The first wiring has a function of applying a first potential to the second subpixel included in the first pixel. The second wiring has a function of applying the first potential to the first subpixel included in the second pixel. The third wiring has a function of applying the first potential to the second subpixel included in the second pixel. The fourth wiring has a function of applying the first potential to the first subpixel included in the third pixel. The first wiring and the second wiring are adjacent to each other. The third wiring and the fourth wiring are adjacent to each other. A distance between the first wiring and the second wiring is shorter than a distance between the third wiring and the fourth wiring.
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公开(公告)号：US20220230573A1
公开(公告)日：2022-07-21
申请号：US17609497
申请日：2020-04-28
发明人： Takashi NAKAGAWA , Takayuki IKEDA , Hidetomo KOBAYASHI , Hideaki SHISHIDO , Shuichi KATSUI , Kiyotaka KIMURA
IPC分类号： G09G3/20
摘要： A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
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公开(公告)号：US20240196650A1
公开(公告)日：2024-06-13
申请号：US18287928
申请日：2022-04-20
IPC分类号： H10K59/121 , H10K59/131
CPC分类号： H10K59/1213 , H10K59/131
摘要： A novel display apparatus is provided. The display apparatus includes a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring extends in a first direction and is supplied with a gate signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a source signal. A gate of the first transistor is electrically connected to the first wiring, one of a source and a drain of the first transistor is electrically connected to the second wiring, and the other of the source and the drain of the first transistor is electrically connected to each gate of the plurality of second transistors. The plurality of second transistors are connected in series or in parallel. The first transistor includes a first semiconductor layer in which current flows in the first direction or the second direction.
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公开(公告)号：US20220350432A1
公开(公告)日：2022-11-03
申请号：US17760603
申请日：2020-09-22
发明人： Kei TAKAHASHI , Hidetomo KOBAYASHI , Hajime KIMURA , Takeshi OSADA , Hideaki SHISHIDO , Kiyotaka KIMURA , Shuichi KATSUI , Takeya HIROSE , Takayuki IKEDA
IPC分类号： G06F3/041 , H01L51/52 , H01L27/12 , H01L51/44 , G09G3/3266 , G06F3/042 , G09G3/3275 , G09G3/3233
摘要： To provide an inexpensive display device. The display device includes a pixel and an IC chip. The pixel includes a first pixel circuit including a display element and a second pixel circuit including a light-receiving device. The one IC chip includes a control circuit, a data driver circuit, and a read circuit. The first and second pixel circuits are electrically connected to the read circuit. The control circuit has a function of controlling driving of the data driver circuit and the read circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The read circuit has a function of outputting a monitor signal corresponding to a monitor current when the monitor current flows through the first pixel circuit. The read circuit also has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.
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公开(公告)号：US20230386383A1
公开(公告)日：2023-11-30
申请号：US18296690
申请日：2023-04-06
发明人： Takashi NAKAGAWA , Takayuki IKEDA , Hidetomo KOBAYASHI , Hideaki SHISHIDO , Shuichi KATSUI , Kiyotaka KIMURA
IPC分类号： G09G3/20
CPC分类号： G09G3/20 , G09G2300/0814 , G09G2310/027 , G09G2310/0297 , G09G2310/08 , H01L27/1225
摘要： A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
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公开(公告)号：US20210318856A1
公开(公告)日：2021-10-14
申请号：US17050359
申请日：2019-04-15
发明人： Takayuki IKEDA , Roh YAMAMOTO , Shuichi KATSUI
IPC分类号： G06F7/60 , H01L27/108 , H01L27/12 , H01L29/786 , G06F7/57 , G06N3/08
摘要： A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.
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公开(公告)号：US20220208939A1
公开(公告)日：2022-06-30
申请号：US17555671
申请日：2021-12-20
IPC分类号： H01L27/32 , H01L29/786
摘要： A display device with high resolution is provided. A display device with low power consumption is provided. A display device with high luminance is provided. A display device with a high aperture ratio is provided. The display device includes a first wiring, a second wiring, a third wiring, and a pixel electrode. The first wiring extends in a first direction and is supplied with a source signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a gate signal. The third wiring is supplied with a constant potential. The first wiring and the pixel electrode overlap with each other with the third wiring therebetween.
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公开(公告)号：US20220181428A1
公开(公告)日：2022-06-09
申请号：US17603067
申请日：2020-04-27
IPC分类号： H01L27/32
摘要： A display apparatus with low power consumption and high image quality is provided. The display apparatus includes a light-emitting element, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. Preferably, one electrode of the light-emitting element is electrically connected to one of a source and a drain of the first transistor; the one electrode of the light-emitting element is electrically connected to one electrode of the first capacitor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor; the gate of the first transistor is electrically connected to one electrode of the second capacitor; the other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor; and the other electrode of the second capacitor is electrically connected to one of a source and a drain of the third transistor.
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公开(公告)号：US20210217891A1
公开(公告)日：2021-07-15
申请号：US17054926
申请日：2019-05-23
IPC分类号： H01L29/786 , H01L29/66 , H01L27/108 , G11C11/4074 , G11C11/4096
摘要： A semiconductor device in which the accuracy of arithmetic operation is increased by correction of the threshold voltage of a transistor can be provided. The semiconductor device includes first and second current supply circuits, and the second current supply circuit has the same configuration as the first current supply circuit. The first current supply circuit includes first and second transistors, a first capacitor, and first to third nodes. A first terminal of the first transistor is electrically connected to the first node, and a back gate of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first capacitor. A gate of the first transistor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor. The first node of the first current supply circuit is electrically connected to a second node of each of the first and second current supply circuits. The threshold voltage of the first transistor is corrected by writing a correction voltage to the back gate of the first transistor.
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