公开(公告)号：US20140253174A1

公开(公告)日：2014-09-11

申请号：US14282288

申请日：2014-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiya TAKEWAKI

IPC: H03K19/0175

CPC classification number: H03K19/017581 ,  H03K19/0948 ,  H03K19/1776 ,  H03K19/17772

Abstract: A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.

Abstract translation: 提供一种逻辑电路，即使在未提供电源电位时也能够保持逻辑电路的开关状态，在供电之后逻辑块的启动时间短，可以以低功耗工作，并且可以 容易地在NAND电路和NOR电路之间切换。 在NAND电路和NOR电路之间的切换是通过包括氧化物半导体的晶体管切换节点处的电荷保持状态来实现的。 通过使用作为晶体管的宽带隙半导体的氧化物半导体材料，可以充分降低晶体管的截止电流; 因此，在节点处保持的电荷状态可以是非易失性的。

公开(公告)号：US20150213842A1

公开(公告)日：2015-07-30

申请号：US14678098

申请日：2015-04-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Yoshiya TAKEWAKI

IPC: G11C5/10 ,  G11C11/4091 ,  G11C11/406

CPC classification number: G11C5/10 ,  G11C11/401 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1218 ,  H01L27/1225

Abstract: In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

Abstract translation: 在包括具有排列成矩阵的存储单元的存储单元阵列的存储器模块中，每个存储单元包括使用氧化物半导体的第一晶体管和第一电容器; 包括p沟道第三晶体管，第二电容器和使用氧化物半导体的第二晶体管的参考单元; 以及包括电阻器和比较器的刷新定时检测电路，其中当通过第一晶体管向第一电容器提供电位时，通过第二晶体管将电位提供给第二电容器，其中第三晶体管的漏极电流值 根据存储在第二电容器中的电位而改变，并且其中当第三晶体管的漏极电流值高于给定值时，执行存储单元阵列和参考单元的刷新操作。