公开(公告)号：US20230371286A1

公开(公告)日：2023-11-16

申请号：US18225186

申请日：2023-07-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC classification number: H10B69/00 ,  H01L29/7869 ,  H01L27/0688 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4085 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20230335605A1

公开(公告)日：2023-10-19

申请号：US18129122

申请日：2023-03-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji KUSUNOKI ,  Susumu KAWASHIMA ,  Hideaki SHISHIDO ,  Tomoaki ATSUMI ,  Motoharu SAITO

IPC: H01L29/417 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L29/7869 ,  H01L27/088 ,  H01L29/78696

Abstract: A novel semiconductor device is provided. The semiconductor device is a single-polarity semiconductor device including a vertical-channel transistor. In the vertical-channel transistor, the higher parasitic capacitance value of the gate-source parasitic capacitance and the gate-drain parasitic capacitance is used as a bootstrap capacitor, which decreases the occupied area of the semiconductor device. The use of an oxide semiconductor for a semiconductor layer of the vertical-channel transistor increases the breakdown voltage between the source and the drain, which can shorten the channel length. In addition, stable operation can be performed even in a high-temperature environment.

公开(公告)号：US20220208794A1

公开(公告)日：2022-06-30

申请号：US17606533

申请日：2020-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Kazuaki OHSHIMA ,  Kazuki TSUDA ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device with a small characteristic variation due to operating temperature is provided. The semiconductor device includes an odd number of stages of inverter circuits that are circularly connected. The inverter circuit includes a first transistor and a second transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, the one of the source and the drain of the first transistor is supplied with a high power supply potential, and the other of the source and the drain of the first transistor is electrically connected to an output terminal out. A gate of the second transistor is electrically connected to an input terminal in, one of a source and a drain of the second transistor is electrically connected to the output terminal out, and the other of the source and the drain of the second transistor is supplied with a low power supply potential. The first transistor and the second transistor include an oxide semiconductor in a semiconductor layer. The first transistor and the second transistor each include a back gate.

公开(公告)号：US20200373302A1

公开(公告)日：2020-11-26

申请号：US16767645

申请日：2018-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Tomoaki ATSUMI ,  Takahiko ISHIZU

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

Abstract: A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.

公开(公告)号：US20190222209A1

公开(公告)日：2019-07-18

申请号：US16362777

申请日：2019-03-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI

IPC: H03K5/24 ,  H01L49/02 ,  H01L27/146 ,  H01L27/108 ,  H01L23/498 ,  G11C5/14 ,  H01L21/78 ,  H01L27/00

CPC classification number: H03K5/2481 ,  G11C5/144 ,  G11C5/145 ,  H01L21/78 ,  H01L23/49844 ,  H01L27/00 ,  H01L27/10805 ,  H01L27/14687 ,  H01L28/00

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

公开(公告)号：US20190189622A1

公开(公告)日：2019-06-20

申请号：US16275380

申请日：2019-02-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/24 ,  G11C11/24 ,  H01L27/06 ,  H01L27/1156 ,  H01L29/786 ,  G11C11/408 ,  G11C11/403 ,  G11C8/14 ,  G11C7/16 ,  H01L27/11551

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-1th sub memory cell.[Selected Drawing] FIG. 8

公开(公告)号：US20190074049A1

公开(公告)日：2019-03-07

申请号：US16103157

申请日：2018-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Junpei SUGAO

IPC: G11C11/4094 ,  H01L27/12 ,  H01L29/786 ,  G11C11/401 ,  G11C11/4096

CPC classification number: G11C11/4094 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/1104 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

公开(公告)号：US20180005668A1

公开(公告)日：2018-01-04

申请号：US15626595

申请日：2017-06-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Kiyoshi KATO ,  Takanori MATSUZAKI

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C5/063 ,  G11C11/403 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097 ,  H01L21/8258 ,  H01L27/0222 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24 ,  H01L29/7869

Abstract: To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.

公开(公告)号：US20170271516A1

公开(公告)日：2017-09-21

申请号：US15451514

申请日：2017-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H01L29/786 ,  G11C16/04 ,  H01L27/11563 ,  H01L29/24 ,  H01L27/11517

CPC classification number: H01L29/7869 ,  G11C11/401 ,  G11C11/404 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0466 ,  G11C2213/79 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24

Abstract: A semiconductor device is provided in which the power consumption can be reduced by reducing the driving voltage and the on-state current can be increased in a period in which a transistor having an extremely low off-state current is brought into an electrically floating state. The semiconductor device comprises a memory cell, a first circuit, and a second circuit. The memory cell includes a first transistor. The first transistor includes a first semiconductor layer, a first gate electrode, and a first back gate electrode. The first gate electrode is connected to a word line. The first back gate electrode is connected to a back gate line. The first circuit supplies a signal for controlling the conduction state of the first transistor to the word line. The second circuit supplies a voltage for controlling the threshold voltage of the first transistor to the back gate line. The second circuit has a function of bringing the back gate line into an electrically floating state in a period in which a signal for controlling the conduction state of the first transistor is supplied to the word line.

公开(公告)号：US20170243874A1

公开(公告)日：2017-08-24

申请号：US15591150

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/24 ,  G11C11/24 ,  H01L29/786

CPC classification number: H01L27/115 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/24 ,  H01L29/7869

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell.