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公开(公告)号：US20190326207A1
公开(公告)日：2019-10-24
申请号：US16464880
申请日：2016-11-30
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00 , H01L21/56 , H01L25/065 , H01L23/538 , H01L23/31
摘要： An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.
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公开(公告)号：US20200043886A1
公开(公告)日：2020-02-06
申请号：US16465233
申请日：2016-11-30
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
摘要： An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.
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公开(公告)号：US11335664B2
公开(公告)日：2022-05-17
申请号：US16465233
申请日：2016-11-30
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
摘要： An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.
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公开(公告)号：US10930634B2
公开(公告)日：2021-02-23
申请号：US16465455
申请日：2016-11-30
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
摘要： An integrated circuit system and a packaging method therefor are disclosed. The method includes providing a first carrier and a second carrier oppositely, with a first device set of the first carrier and a second device set of the second carrier both located between the first and second carriers, providing a molding material between the first and second carriers to make the first and second device sets respectively in contact with the molding material, curing the material to make the first and second device sets respectively mounted at two sides of the molding material, making the first and second carriers detached from the first device set and the molding material and from the second device set and the molding material respectively; and forming connection holes in the molding material and fabricating a conductive layer which extend into the connection holes to electrically connect the first and second device sets.
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公开(公告)号：US20190287909A1
公开(公告)日：2019-09-19
申请号：US16464896
申请日：2016-11-30
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
IPC分类号： H01L23/538 , H01L23/367 , H01L23/31 , H01L23/552 , H01L21/48 , H01L21/56
摘要： An integrated circuit packaging structure and method are provided, the integrated circuit packaging structure includes: a substrate, the substrate being provided with a circuit layer and fine wiring; a chip, the chip being provided with a fine pin and a chip pin; the substrate is provided with at least two of said chips, a chip pin of at least one of said chips being electrically connected to the circuit layer; an insulation patch, the fine wiring being provided on the insulation patch, while the fine pin of the chip is electrically connected to the fine wiring, at least two of said chips being directly electrically connected by means of the fine wiring.
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公开(公告)号：US11183458B2
公开(公告)日：2021-11-23
申请号：US16464896
申请日：2016-11-30
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
IPC分类号： H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/552 , H01L25/065 , H01L25/11 , H01L25/07 , H01L25/075
摘要： An integrated circuit packaging structure and method are provided, the integrated circuit packaging structure includes: a substrate, the substrate being provided with a circuit layer and fine wiring; a chip, the chip being provided with a fine pin and a chip pin; the substrate is provided with at least two of said chips, a chip pin of at least one of said chips being electrically connected to the circuit layer; an insulation patch, the fine wiring being provided on the insulation patch, while the fine pin of the chip is electrically connected to the fine wiring, at least two of said chips being directly electrically connected by means of the fine wiring.
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公开(公告)号：US20190326261A1
公开(公告)日：2019-10-24
申请号：US16465229
申请日：2016-11-30
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
IPC分类号： H01L25/065 , H01L23/498 , H01L23/00 , H01L23/31 , H01L25/00 , H01L21/48 , H01L25/10
摘要： An integrated circuit multichip stacked packaging structure and method, including: first pins, provided at bottom surface of first chip; second pins, provided at top surface of second chip; circuit layers, provided at top surface of substrate, and/or circuit layers, provided at bottom surface of substrate, and/or circuit layers, provided within substrate; first chip, provided at top surface of substrate; second chip, provided at top surface of first chip; first pin is electrically connected at least to one of circuit layers provided with circuit pins, substrate is provided with connecting through hole, which is docked with circuit pin, first opening thereof is docked with first pin, second opening thereof is operating window, electrically-conductive layer is provided within connecting through hole, and electrically connects first pin to circuit pin; second pin is electrically connected at least to one of circuit layers; second pin is electrically connected to circuit layer via electrically-conductive layer.
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