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公开(公告)号:US20110066795A1
公开(公告)日:2011-03-17
申请号:US12829345
申请日:2010-07-01
申请人: XIU-LI GUO , JIIN LAI , ZHI-QIANG HUI , SHUANG-SHUANG QIN
发明人: XIU-LI GUO , JIIN LAI , ZHI-QIANG HUI , SHUANG-SHUANG QIN
CPC分类号: G06F12/0862 , G06F12/0875 , G06F12/10 , G06F2212/6028
摘要: The present invention is directed to a stream context cache system, which primarily includes a cache and a mapping table. The cache stores plural stream contexts, and the mapping table stores associated stream context addresses in a system memory. Consequently, a host may, according to the content of the mapping table, directly retrieve the stream context that is pre-fetched and stored in the cache, rather than read the stream context from the system memory.
摘要翻译: 本发明涉及一种流上下文高速缓存系统,其主要包括高速缓存和映射表。 高速缓存存储多个流上下文,并且映射表将相关联的流上下文地址存储在系统存储器中。 因此,主机可以根据映射表的内容直接检索预取和存储在高速缓存中的流上下文,而不是从系统存储器读取流上下文。
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公开(公告)号:US20110066812A1
公开(公告)日:2011-03-17
申请号:US12829343
申请日:2010-07-01
申请人: SHUANG-SHUANG QIN , JIIN LAI , ZHI-QIANG HUI , XIU-LI GUO
发明人: SHUANG-SHUANG QIN , JIIN LAI , ZHI-QIANG HUI , XIU-LI GUO
IPC分类号: G06F12/08
CPC分类号: G06F12/0862
摘要: The present invention is directed to a transfer request block (TRB) cache system and method. A cache is used to store plural TRBs, and a mapping table is utilized to store corresponding TRB addresses in a system memory. A cache controller pre-fetches the TRBs and stores them in the cache according to the content of the mapping table.
摘要翻译: 本发明涉及一种传输请求块(TRB)高速缓存系统和方法。 高速缓存用于存储多个TRB,并且利用映射表将对应的TRB地址存储在系统存储器中。 缓存控制器根据映射表的内容预取TRB并将其存储在缓存中。
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公开(公告)号:US20110066785A1
公开(公告)日:2011-03-17
申请号:US12694470
申请日:2010-01-27
申请人: JIAN LI , JIIN LAI , SHAN-NA PANG , ZHI-QIANG HUI , DI DAI
发明人: JIAN LI , JIIN LAI , SHAN-NA PANG , ZHI-QIANG HUI , DI DAI
CPC分类号: G06F12/1036
摘要: A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.
摘要翻译: 存储器管理系统和方法包括并使用高速缓冲存储器(例如,表查看缓冲器,TLB),存储器映射表,暂存器缓存和存储器控制器。 高速缓存缓冲器被配置为存储多个数据结构。 存储器映射表被配置为存储数据结构的多个地址。 暂存器缓存被配置为存储数据结构的基址。 存储器控制器被配置为控制高速缓冲存储器和暂存器缓存中的读写。 这些组件在存储器控制器的控制下一起可操作,以便有效地搜索存储器管理系统中的数据结构。
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