Charge pump calibration for dual-path phase-locked loop
    1.
    发明授权
    Charge pump calibration for dual-path phase-locked loop 有权
    双路锁相环的电荷泵校准

    公开(公告)号:US09225345B2

    公开(公告)日:2015-12-29

    申请号:US14371973

    申请日:2014-01-30

    CPC classification number: H03L7/0898 H03L7/0893 H03L7/0992 H03L7/0994

    Abstract: Embodiments of the invention are generally directed to charge pump calibration for a dual-path phase-locked loop circuit. An embodiment of an apparatus includes a phase frequency detector; an integral path including a first charge pump; a proportional path including a second charge pump; and a calibration mechanism for the first charge pump and the second charge pump, the calibration mechanism including a phase detector to detect whether a reference clock signal or a feedback clock signal is leading or lagging in phase and to generate a signal indicating which clock signal is leading or lagging, a first memory element and a second memory element to store the signal from the phase detector, a first control logic to adjust current for the first charge pump based on the value stored in the first memory element, and a second control logic to adjust current for the second charge pump based on the value stored in the second memory element.

    Abstract translation: 本发明的实施例一般涉及用于双路锁相环电路的电荷泵校准。 装置的实施例包括相位频率检测器; 包括第一电荷泵的整体路径; 包括第二电荷泵的比例路径; 以及用于所述第一电荷泵和所述第二电荷泵的校准机构,所述校准机构包括相位检测器,用于检测参考时钟信号或反馈时钟信号是否在同相中前进或滞后,并产生指示哪个时钟信号为 第一存储器元件和第二存储器元件,用于存储来自相位检测器的信号;第一控制逻辑,用于基于存储在第一存储器元件中的值来调整第一电荷泵的电流;以及第二控制逻辑 基于存储在第二存储元件中的值来调整第二电荷泵的电流。

    Charge Pump Calibration for Dual-Path Phase-Locked Loop
    2.
    发明申请
    Charge Pump Calibration for Dual-Path Phase-Locked Loop 有权
    双路锁相环电荷泵校准

    公开(公告)号:US20150214966A1

    公开(公告)日:2015-07-30

    申请号:US14371973

    申请日:2014-01-30

    CPC classification number: H03L7/0898 H03L7/0893 H03L7/0992 H03L7/0994

    Abstract: Embodiments of the invention are generally directed to charge pump calibration for a dual-path phase-locked loop circuit. An embodiment of an apparatus includes a phase frequency detector; an integral path including a first charge pump; a proportional path including a second charge pump; and a calibration mechanism for the first charge pump and the second charge pump, the calibration mechanism including a phase detector to detect whether a reference clock signal or a feedback clock signal is leading or lagging in phase and to generate a signal indicating which clock signal is leading or lagging, a first memory element and a second memory element to store the signal from the phase detector, a first control logic to adjust current for the first charge pump based on the value stored in the first memory element, and a second control logic to adjust current for the second charge pump based on the value stored in the second memory element.

    Abstract translation: 本发明的实施例一般涉及用于双路锁相环电路的电荷泵校准。 装置的实施例包括相位频率检测器; 包括第一电荷泵的整体路径; 包括第二电荷泵的比例路径; 以及用于所述第一电荷泵和所述第二电荷泵的校准机构,所述校准机构包括相位检测器,用于检测参考时钟信号或反馈时钟信号是否在同相中前进或滞后,并产生指示哪个时钟信号为 第一存储器元件和第二存储器元件,用于存储来自相位检测器的信号;第一控制逻辑,用于基于存储在第一存储器元件中的值来调整第一电荷泵的电流;以及第二控制逻辑 基于存储在第二存储元件中的值来调整第二电荷泵的电流。

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