公开(公告)号：US11941246B2

公开(公告)日：2024-03-26

申请号：US17506414

申请日：2021-10-20

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: Disclosed are a data processing system comprising: a memory system for providing a host with a memory map segment including map pieces; and the host for storing the memory map segment as a host map segment and converting a logical address into a physical address using the host map segment. The memory system stores changed map pieces in a map cache, inserts the changed map pieces in a response to a first command, and provides the host with the response. The host updates the host map segment based on the changed map pieces. When a read command includes a logical address and a physical address, the memory system accesses a memory device using the physical address of the read command according to whether the logical address of the read command is stored in the map cache.

公开(公告)号：US11853202B2

公开(公告)日：2023-12-26

申请号：US17307868

申请日：2021-05-04

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/02 ,  G06F12/0891

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/0891 ,  G06F2212/7201

Abstract: An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.

公开(公告)号：US11775211B2

公开(公告)日：2023-10-03

申请号：US17182008

申请日：2021-02-22

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: The present technology relates to an electronic device. A memory controller according to the present technology may include a host interface controller, a plurality of buffers, and a memory operation controller. The host interface controller may sequentially generate a plurality of commands based on a request received from a host. The plurality of buffers may store the plurality of commands according to command attributes. The memory operation controller may compare a sequence number of a target command stored in a target buffer among the plurality of buffers with a sequence number of a standby command stored in remaining buffers, and may determine a process of the target command and a process of the standby command based on a comparison. wherein a buffer satisfying a flush condition among the plurality of buffers is selected as the target buffer.

公开(公告)号：US11182289B1

公开(公告)日：2021-11-23

申请号：US17015306

申请日：2020-10-13

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0811 ,  G06F12/0804

Abstract: A memory system is provided to include memory devices and a controller including cores controlling the memory devices, respectively. The controller determines whether to perform a global wear-leveling operation based on a write count of the plurality of memory devices corresponding to each of the plurality of cores, performs a barrier operation for a request from a host when the global wear-leveling operation is determined to be performed, updates mapping information for mapping a core to memory device information by swapping the mapping information between different cores based on the write count of each of the plurality of cores and closes an open block assigned to each of the plurality of cores and then assigning a new open block to each of the plurality of cores based on the updated mapping information.

公开(公告)号：US12026092B2

公开(公告)日：2024-07-02

申请号：US17849194

申请日：2022-06-24

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/06 ,  G06F12/0817

CPC classification number: G06F12/0646 ,  G06F12/082

Abstract: A data storage device may include a storage and a controller. The storage a storage including a first region of a first physical address range and a second region of a second physical address range. The controller may generate map data including a plurality of map segments, a first segment entry and a second segment entry, and store, in the second region, the map data except for a first map segment. Each of the map segments includes a set of physical addresses corresponding to a plurality of sequential logical addresses. The first segment entry includes a first segment physical address associated with the first map segment and belonging to the first physical address range, and the second segment entry includes a second segment physical address associated with a second map segment and belonging to the second physical address range.

公开(公告)号：US11567860B2

公开(公告)日：2023-01-31

申请号：US17217242

申请日：2021-03-30

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F12/02 ,  G06F12/0831 ,  G06F12/0884 ,  G06F12/123

Abstract: A memory system includes a storage medium and a controller. The storage medium includes a plurality of memory regions. The controller stores data corresponding to a write request into a memory region of a random attribute or a memory region of a sequential attribute among the memory regions and to update logical-to-physical (L2P) information corresponding to the stored data, and updates, when storing the data into the memory region of the random attribute, physical-to-logical (P2L) information corresponding to the stored data within a P2L table of the memory region of the random attribute.

公开(公告)号：US11520519B2

公开(公告)日：2022-12-06

申请号：US16513470

申请日：2019-07-16

Applicant: SK hynix Inc.

Inventor： Byung Jun Kim ,  Eu Joon Byun ,  Hye Mi Kang

IPC: G06F3/06

Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller may include a command processor configured to generate a flush command in response to a flush request and determine flush data chunks to be stored, a write operation controller configured to control memory devices to perform a first program operation of storing flush data chunks, and to perform a second program operation of storing data corresponding to a write request that is input later than the flush request, regardless of whether a response to the flush command has been provided to a host, and a flush response controller configured to, when the first program operation is completed, provide a response to the flush command to the host depending on whether responses to flush commands, input earlier than the flush command, have been provided to the host.

公开(公告)号：US20220171532A1

公开(公告)日：2022-06-02

申请号：US17304076

申请日：2021-06-14

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang

IPC: G06F3/06

Abstract: An electronic system includes a file system configured to assign logical block addresses corresponding to consecutive pieces of data sets of segments in a plurality of zones. The electronic system also includes a memory device including a plurality of memory blocks, and a memory controller configured to map the logical block addresses to physical block addresses corresponding to consecutive pages in the plurality of memory blocks to program the consecutive pieces of data to the consecutive pages in the plurality of memory blocks. The file system is configured to assign new logical block addresses corresponding to consecutive pieces of a data file to invalid segments in the plurality of zones.

公开(公告)号：US11194736B2

公开(公告)日：2021-12-07

申请号：US16582822

申请日：2019-09-25

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/122 ,  G06F12/10

Abstract: A memory controller may include a map cache configured to store one or more of a plurality of map data sub-segments respectively corresponding to a plurality of sub-areas included in each of the plurality of areas, and a map data manager configured to generate information about a map data sub-segment to be provided to a host and which is determined based on a read count for the memory device, and generate information about a map data segment to be deleted from the host and which is determined based on the read count for the memory device and a memory of the host.

公开(公告)号：US12287977B2

公开(公告)日：2025-04-29

申请号：US18402721

申请日：2024-01-02

Applicant: SK hynix Inc.

Inventor： Sae Gyeol Choi ,  Hye Mi Kang

IPC: G06F3/06

Abstract: A storage device may dynamically allocate, to a buffer, at least one among M number of buffer units each capable of storing at least one of a plurality of L2P mapping units. When receiving, from an external device, a mapping unit command requesting one or more target L2P mapping units among the plurality of L2P mapping units, the storage device may store the target L2P mapping units in the buffer before transmitting the target L2P mapping units to the external device.