公开(公告)号：US12099751B2

公开(公告)日：2024-09-24

申请号：US18046832

申请日：2022-10-14

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673

Abstract: A memory system, a memory controller, and an operating method of the memory system are provided. The memory system may include a memory device including a first type memory block and a second type memory block and a memory controller configured to determine, when receiving a command to set a read boost mode for the target logical address, whether the data corresponding to the target logical address can be copied from the first type memory block to the second type memory block, and copy the data corresponding to the target logical address from the first type memory block to the second type memory block.

公开(公告)号：US11656996B2

公开(公告)日：2023-05-23

申请号：US17186542

申请日：2021-02-26

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/0882 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0882 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0238

Abstract: A memory system includes a memory device comprising a plurality of pages, and a controller suitable for storing data, inputted in response to a write command received from a host, in corresponding pages among the plurality of pages, wherein the controller generates and manages a bitmap table indicating order information of the inputted data according to the type of the write command.

公开(公告)号：US11520519B2

公开(公告)日：2022-12-06

申请号：US16513470

申请日：2019-07-16

Applicant: SK hynix Inc.

Inventor： Byung Jun Kim ,  Eu Joon Byun ,  Hye Mi Kang

IPC: G06F3/06

Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller may include a command processor configured to generate a flush command in response to a flush request and determine flush data chunks to be stored, a write operation controller configured to control memory devices to perform a first program operation of storing flush data chunks, and to perform a second program operation of storing data corresponding to a write request that is input later than the flush request, regardless of whether a response to the flush command has been provided to a host, and a flush response controller configured to, when the first program operation is completed, provide a response to the flush command to the host depending on whether responses to flush commands, input earlier than the flush command, have been provided to the host.

公开(公告)号：US11379133B2

公开(公告)日：2022-07-05

申请号：US17022564

申请日：2020-09-16

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06 ,  G06F1/32 ,  G06F1/3296 ,  G06F1/3234

Abstract: An electronic device may include a plurality of data storage devices including a master storage device and one or more slave storage devices. Each of the data storage devices comprises a storage configured to store data and a controller configured to control data input/output operations with respect to the corresponding storage. The controller of the master storage device receives device information including identification information, capacity information and physical configuration information from each of the slave storage devices, and the controller of the master storage device changes an electric power mode of at least one of the slave storage devices selected based on capacity margin of the master storage device and the device information.

公开(公告)号：US11269767B2

公开(公告)日：2022-03-08

申请号：US16692615

申请日：2019-11-22

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/02 ,  G06F3/06

Abstract: A memory controller for performing garbage collection without moving data of a valid page, controls a memory device including a plurality of memory blocks in which data is stored. The memory controller includes a victim block setting circuit for selecting a victim block among the memory blocks by receiving memory block information representing whether a valid page and an invalid page are included in each of the plurality of memory blocks, when garbage collection is performed, and a sub-block controller for outputting a sub-block read command for determining valid pages included in each of sub-blocks within the victim block, by dividing the victim block into the sub-blocks, and outputting a sub-block erase command for selectively erasing a part of the sub-blocks included in the victim block, by receiving sub-block information corresponding to the sub-block read command from the memory device.

公开(公告)号：US11263148B2

公开(公告)日：2022-03-01

申请号：US16936779

申请日：2020-07-23

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/1009

Abstract: A memory system is provided to include a first storage device including a first memory device and a first memory controller configured to receive, from a host external to the first storage device, a request including a logical address corresponding to the request; and a second storage device including a second memory device and a second memory controller coupled to receive a request from the first storage device and to control the second memory device, wherein the first memory controller is configured to select a target address among candidate addresses and map the logical address received from the host to the target address, and wherein the candidate addresses include first physical addresses corresponding to the first memory blocks and virtual addresses corresponding to the second memory blocks included in the second memory device.

公开(公告)号：US11194736B2

公开(公告)日：2021-12-07

申请号：US16582822

申请日：2019-09-25

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/122 ,  G06F12/10

Abstract: A memory controller may include a map cache configured to store one or more of a plurality of map data sub-segments respectively corresponding to a plurality of sub-areas included in each of the plurality of areas, and a map data manager configured to generate information about a map data sub-segment to be provided to a host and which is determined based on a read count for the memory device, and generate information about a map data segment to be deleted from the host and which is determined based on the read count for the memory device and a memory of the host.

公开(公告)号：US11163491B2

公开(公告)日：2021-11-02

申请号：US16577369

申请日：2019-09-20

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

Abstract: Provided herein is a memory system and a method of operating the memory system. The memory system may include: a memory device including a plurality of memory blocks; and a controller configured to control the memory device to perform a read operation in response to a host command, and configured to control a read reclaim operation based on a read count of each of the plurality of memory blocks. During the read reclaim operation, the controller may select a program mode of a target memory block depending on the amount of valid data read from a victim memory block, and control the memory device to store the valid data in the target memory block based on the selected program mode.

公开(公告)号：US11119938B2

公开(公告)日：2021-09-14

申请号：US16665665

申请日：2019-10-28

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/10

Abstract: A data storage device may include: a controller, including a host memory and a device memory, configured to communicate with a host, wherein one or more host unit regions, having a first size, are allocated to the host memory; and a storage including a nonvolatile memory device. The controller may include a map data manager configured to store map data in the storage, the map data including a mapping relationship between logical addresses of the host and physical addresses of the data storage device, configured to group the logical addresses into logical address groups so that the total size of map data for each of the logical address groups corresponds to the first size, and manage a reference count for each of the logical address groups.

公开(公告)号：US20200226070A1

公开(公告)日：2020-07-16

申请号：US16569536

申请日：2019-09-12

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/1009

Abstract: A memory controller may include: a map data processor configured to receive original map data segments from a memory device and generate a mode signal; an original map data storage configured to sequentially store the original map data segments in source storage areas corresponding to source addresses; a converted map data storage configured to store the original map data segments in target storage areas corresponding to target addresses; and a map data converter configured to control the converted map data storage such that, when any one original map data segment is stored in a first target storage area corresponding to a first target address, an original map data segment subsequent to the any one original map data segment is stored in a second target storage area corresponding to a second target address obtained by adding a predetermined offset to the first target address.