公开(公告)号：US20200168795A1

公开(公告)日：2020-05-28

申请号：US16777608

申请日：2020-01-30

Applicant: SK hynix Inc.

Inventor： Kyoung Su CHOI

IPC: H01L45/00 ,  H01L27/24 ,  G11C8/14 ,  G11C7/18

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.

公开(公告)号：US20150200358A1

公开(公告)日：2015-07-16

申请号：US14261533

申请日：2014-04-25

Applicant: SK hynix Inc.

Inventor： Se Hun KANG ,  Jin Ha KIM ,  Kang Sik CHOI ,  Deok Sin KIL ,  Gyu Hyun KIM ,  Kyoung Su CHOI ,  Sung Bin HONG ,  Jung Won SEO

IPC: H01L45/00 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1683

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a lower electrode disposed on the semiconductor substrate wherein an upper surface of the lower electrode has a recess, an interlayer insulating layer disposed on the semiconductor substrate and the lower electrode, the interlayer insulating layer including a variable resistive region exposing the upper surface of the lower electrode, and a variable resistive layer filled in the variable resistive region that contacts the recess of the lower electrode. The variable resistive layer is formed to have an increased width toward a top and a bottom thereof.

Abstract translation: 半导体集成电路器件包括半导体衬底，设置在半导体衬底上的下电极，其中下电极的上表面具有凹部，设置在半导体衬底上的层间绝缘层和下电极，所述层间绝缘层包括： 暴露下部电极的上表面的可变电阻区域和填充在与下部电极的凹部接触的可变电阻区域中的可变电阻层。 可变电阻层形成为朝向其顶部和底部具有增加的宽度。

公开(公告)号：US20190181341A1

公开(公告)日：2019-06-13

申请号：US16107338

申请日：2018-08-21

Applicant: SK hynix Inc.

Inventor： Kyoung Su CHOI

IPC: H01L45/00 ,  H01L27/24 ,  G11C7/18 ,  G11C8/14

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.