-
公开(公告)号:US20190252609A1
公开(公告)日:2019-08-15
申请号:US16329294
申请日:2017-09-12
发明人: HIROAKI SEI , KAZUHIRO OHBA , TAKEYUKI SONE , SEIJI NONOGUCHI , MINORU IKARASHI
CPC分类号: H01L45/141 , H01L21/8239 , H01L27/105 , H01L27/224 , H01L27/2427 , H01L27/2481 , H01L45/00 , H01L45/06 , H01L45/147 , H01L49/00
摘要: A switch device according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).
-
公开(公告)号:US20190180820A1
公开(公告)日:2019-06-13
申请号:US16274521
申请日:2019-02-13
发明人: Yuniarto Widjaja
IPC分类号: G11C14/00 , G11C11/407 , G11C11/21 , G11C13/00 , H01L45/00 , H01L27/24 , H01L27/108 , H01L29/78 , G11C11/404 , G11C11/4072
CPC分类号: G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
-
公开(公告)号:US20180358410A1
公开(公告)日:2018-12-13
申请号:US15986932
申请日:2018-05-23
申请人: SK hynix Inc.
发明人: Sanghun LEE
CPC分类号: H01L27/2463 , G11C11/22 , G11C13/0007 , G11C13/0069 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
摘要: A resistance change memory device includes a lower electrode, a ferroelectric material layer disposed on the lower electrode, a resistance switching material layer disposed on the ferroelectric material layer, and an upper electrode disposed on the resistance switching material layer.
-
公开(公告)号:US20180351095A1
公开(公告)日:2018-12-06
申请号:US15778776
申请日:2016-11-23
IPC分类号: H01L45/00
CPC分类号: H01L45/1625 , H01L45/08 , H01L45/147
摘要: A memristor device is disclosed comprising: a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour. A method of fabricating a memristor device is also disclosed.
-
公开(公告)号:US20180330790A1
公开(公告)日:2018-11-15
申请号:US16017249
申请日:2018-06-25
发明人: Yuniarto Widjaja
IPC分类号: G11C14/00 , H01L27/102 , H01L45/00 , H01L27/12 , G11C13/00 , G11C11/402 , G11C11/4067
CPC分类号: G11C14/0045 , G06F3/0619 , G06F3/0647 , G06F3/0685 , G11C11/14 , G11C11/4026 , G11C11/404 , G11C11/4067 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0078 , G11C2211/4016 , G11C2211/5643 , G11C2213/31 , G11C2213/32 , H01L27/1023 , H01L27/108 , H01L27/10802 , H01L27/10897 , H01L27/1203 , H01L27/24 , H01L27/2445 , H01L27/2463 , H01L29/7841 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147
摘要: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
-
公开(公告)号:US20180315796A1
公开(公告)日:2018-11-01
申请号:US15828014
申请日:2017-11-30
申请人: SK hynix Inc.
发明人: Jong Chul LEE , Jongho LEE
IPC分类号: H01L27/24 , H01L23/528 , H01L45/00 , H01L43/02 , H01L43/08 , H01L43/12 , H01L27/22 , H01L43/10
CPC分类号: H01L27/2463 , H01L23/528 , H01L27/224 , H01L27/2409 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/165 , H01L45/1675
摘要: A method of manufacturing a cross-point memory array device is disclosed. In the method, a substrate is provided. A plurality of first conductive line patterns are formed over the substrate. An insulating layer is formed over the first conductive line patterns. The insulating layer includes an insulative oxide. A plurality of switching film patterns are formed on the first conductive line patterns by selectively doping a plurality regions of the insulating layer. A plurality of memory structures are formed on the plurality of switching film patterns, respectively. A plurality of second conductive line patterns are formed on the plurality of memory structures.
-
公开(公告)号:US20180308900A1
公开(公告)日:2018-10-25
申请号:US16017811
申请日:2018-06-25
发明人: Daniel BEDAU
IPC分类号: H01L27/24 , H01L45/00 , H01L23/528
CPC分类号: H01L27/2463 , H01L23/528 , H01L45/04 , H01L45/08 , H01L45/1206 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1608
摘要: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.
-
公开(公告)号:US20180269390A1
公开(公告)日:2018-09-20
申请号:US15707028
申请日:2017-09-18
CPC分类号: H01L45/085 , H01L27/2481 , H01L45/1233 , H01L45/1266 , H01L45/147 , H01L45/1616 , H01L45/1641
摘要: A memory device according to an embodiment includes a first conductive layer, a second conductive layer; and a first metal oxide layer provided between the first conductive layer and the second conductive layer. The first metal oxide layer includes titanium oxide, the first metal oxide layer has a first region and a second region, a mole fraction of anatase titanium oxide in the titanium oxide of the first region is a first mole fraction, and a mole fraction of anatase titanium oxide in the titanium oxide of the second region is a second mole fraction lower than the first mole fraction.
-
公开(公告)号:US20180247946A1
公开(公告)日:2018-08-30
申请号:US15969680
申请日:2018-05-02
申请人: SK hynix Inc.
发明人: Hyung-Dong LEE
IPC分类号: H01L27/11521 , G06N3/063 , H01L27/11519 , H01L27/11556
CPC分类号: G06N3/063 , G11C11/54 , G11C16/0416 , G11C16/10 , H01L21/28282 , H01L21/28291 , H01L27/11519 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/141 , H01L45/146 , H01L45/147
摘要: A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first direction; a plurality of column lines extending in a second direction that crosses the first direction; and a plurality of synapses positioned at intersections of the row lines, the additional row lines, and the column lines, wherein each of the synapses includes a transistor comprising a floating gate, a control gate insulated from the floating gate, a first junction, and a second junction, the control gate being coupled to a corresponding one of the plurality of row lines, the first junction being coupled to a corresponding one of the plurality of additional row lines, the second junction being coupled to a corresponding one of the plurality of column lines.
-
公开(公告)号:US10056120B2
公开(公告)日:2018-08-21
申请号:US15676700
申请日:2017-08-14
CPC分类号: G11C5/063 , G11C5/025 , G11C5/06 , G11C8/08 , H01L21/76838 , H01L27/0207 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147
摘要: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
-
-
-
-
-
-
-
-
-