公开(公告)号：US20210074339A1

公开(公告)日：2021-03-11

申请号：US16809266

申请日：2020-03-04

Applicant: SK hynix Inc.

Inventor： Kyung Ho CHU ,  Soo Bin LIM ,  Yong Suk JOO

IPC: G11C7/12 ,  G11C7/08 ,  G11C7/22 ,  G11C7/10

Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.

公开(公告)号：US20210280227A1

公开(公告)日：2021-09-09

申请号：US17331368

申请日：2021-05-26

Applicant: SK hynix Inc.

Inventor： Kyung Ho CHU ,  Soo Bin LIM ,  Yong Suk JOO

IPC: G11C7/12 ,  G11C7/08 ,  G11C7/10 ,  G11C7/22

Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.

公开(公告)号：US20190385689A1

公开(公告)日：2019-12-19

申请号：US16216748

申请日：2018-12-11

Applicant: SK hynix Inc.

Inventor： Soo Young JANG ,  Kyu Bong KONG ,  Geun Il LEE ,  Yong Suk JOO ,  Kyung Ho CHU

IPC: G11C29/10 ,  G11C29/52 ,  G11C7/10

Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.