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    CLOCK DISTRIBUTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE CLOCK DISTRIBUTION CIRCUIT
    2.
    发明申请
    CLOCK DISTRIBUTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE CLOCK DISTRIBUTION CIRCUIT 审中-公开

    公开(公告)号：US20200293082A1

    公开(公告)日：2020-09-17

    申请号：US16890717

    申请日：2020-06-02

    Applicant: SK hynix Inc.

    Inventor： Soo Young JANG ,  Dae Han KWON ,  Geun Il LEE ,  Kyu Dong HWANG

    IPC: G06F1/10 ,  H03L7/189 ,  H03K19/0185

    Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

    SEMICONDUCTOR APPARATUS
    3.
    发明申请
    SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20160164501A1

    公开(公告)日：2016-06-09

    申请号：US14665957

    申请日：2015-03-23

    Applicant: SK hynix Inc.

    Inventor： Kyu Bong KONG ,  Geun Il LEE

    IPC: H03K3/037 ,  H03K21/02 ,  H03K3/356

    CPC classification number: H03K3/0375 ,  G11C7/1039 ,  G11C7/1087 ,  G11C7/1093 ,  H03K21/026

    Abstract: A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.

    Abstract translation: 一种半导体装置，包括管输入输出信号生成块，其被配置为根据管道使能信号生成多个管输入信号和多个管输出信号，并根据误差检测信号进行初始化; 一个包括多个管道锁存器的管道锁存器组，所述多个管道锁存器中的每一个被配置为根据相应的管道输入信号接收和存储输入信号，并根据相应的管道输出信号输出存储的信号作为输出信号 ; 以及错误检测块，被配置为根据管道端信号，管道使能信号，多个管道输入信号和多个管道输出信号产生误差检测信号。

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM 审中-公开
    半导体器件和半导体系统

    公开(公告)号：US20160260470A1

    公开(公告)日：2016-09-08

    申请号：US14717072

    申请日：2015-05-20

    Applicant: SK hynix Inc.

    Inventor： Jung Hwan JI ,  Geun Il LEE

    IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/406

    CPC classification number: G11C11/4096 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067

    Abstract: A semiconductor system may include a first semiconductor configured to output a command signal and an address signal. The semiconductor system may include a second semiconductor device configured to include a first operation circuit including a first MOS transistor and a second operation circuit including a second MOS transistor. The first MOS transistor and the second MOS transistor may be turned on in response to a first internal command signal when a first operation is executed according to the command signal. The first MOS transistor may be turned on in response to a period signal generated from the address signal when a second operation is executed according to the command signal.

    Abstract translation: 半导体系统可以包括被配置为输出命令信号和地址信号的第一半导体。 半导体系统可以包括第二半导体器件，其被配置为包括包括第一MOS晶体管的第一操作电路和包括第二MOS晶体管的第二操作电路。 当根据命令信号执行第一操作时，第一MOS晶体管和第二MOS晶体管可以响应于第一内部命令信号而导通。 当根据命令信号执行第二操作时，第一MOS晶体管可以响应于从地址信号产生的周期信号而导通。

    SEMICONDUCTOR APPARATUS AND TEST SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS
    8.
    发明申请
    SEMICONDUCTOR APPARATUS AND TEST SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS 审中-公开

    公开(公告)号：US20190385689A1

    公开(公告)日：2019-12-19

    申请号：US16216748

    申请日：2018-12-11

    Applicant: SK hynix Inc.

    Inventor： Soo Young JANG ,  Kyu Bong KONG ,  Geun Il LEE ,  Yong Suk JOO ,  Kyung Ho CHU

    IPC: G11C29/10 ,  G11C29/52 ,  G11C7/10

    Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.

    OPERATION CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OPERATION CONTROL CIRCUIT
    9.
    发明申请
    OPERATION CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OPERATION CONTROL CIRCUIT 审中-公开

    公开(公告)号：US20190318778A1

    公开(公告)日：2019-10-17

    申请号：US16189590

    申请日：2018-11-13

    Applicant: SK hynix Inc.

    Inventor： I Yeong JUNG ,  Geun Il LEE

    IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/10

    Abstract: A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered.

    CLOCK GENERATION CIRCUIT AND CLOCK GENERATION SYSTEM USING THE SAME
    10.
    发明申请
    CLOCK GENERATION CIRCUIT AND CLOCK GENERATION SYSTEM USING THE SAME 有权
    使用该时钟产生电路和时钟发生系统

    公开(公告)号：US20140176209A1

    公开(公告)日：2014-06-26

    申请号：US13845586

    申请日：2013-03-18

    Applicant: SK HYNIX INC.

    Inventor： Jung Hwan JI ,  Geun Il LEE

    IPC: H03L7/099

    CPC classification number: G06F1/08

    Abstract: A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.

    Abstract translation: 时钟发生电路包括计数代码生成单元，被配置为当使能信号有效时产生与输入时钟的频率相对应的计数代码; 控制代码生成单元，被配置为对计数代码进行解码并生成控制代码; 以及循环可变振荡单元，其被配置为响应于所述控制代码来确定输出时钟的频率。

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