公开(公告)号：US20200327063A1

公开(公告)日：2020-10-15

申请号：US16844652

申请日：2020-04-09

申请人： SK hynix Inc.

发明人： Hye-Mi KANG ,  Eu-Joon BYUN ,  Byung-Jun KIM ,  Seok-Jun LEE

IPC分类号： G06F12/0873 ,  G06F12/02 ,  G06F12/0864 ,  G06F13/16 ,  G06F11/30

摘要： A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

公开(公告)号：US20200310692A1

公开(公告)日：2020-10-01

申请号：US16676201

申请日：2019-11-06

申请人： SK hynix Inc.

发明人： Seok-Jun LEE

IPC分类号： G06F3/06

摘要： A memory system includes a memory device including memory blocks and a memory controller configured to control the memory device. The memory device stores a firmware which includes binaries, and the binaries include a first binary and a second binary. The memory controller loads the firmware to a first region in a working memory, loads the first binary to a second region which is included in the first region, and loads the second binary to a third region which is included in the first region and is different from the second region. The memory controller stores information on an entry function corresponding to a target function included in the second binary, in a fourth region which is different from the first region. A start address of the second region is determined as a fixed value, and a start address of the third region is dynamically determined.

公开(公告)号：US20210064242A1

公开(公告)日：2021-03-04

申请号：US16844002

申请日：2020-04-09

申请人： SK hynix Inc.

发明人： Seok-Jun LEE

IPC分类号： G06F3/06

摘要： A memory system comprising: a memory device including a plurality of memory blocks; and a controller suitable for: periodically generating, based on system information periodically inputted from a host, performance information indicating whether an internal operation to be performed on the plurality of memory blocks without a command inputted from the host is performable; accumulatively storing the generated performance information; determining whether the internal operation is performable within a period subsequent to a current period based on the accumulated performance information; and performing the internal operation on the memory blocks during the subsequent period according to a result of the determination.

公开(公告)号：US20210011642A1

公开(公告)日：2021-01-14

申请号：US16776117

申请日：2020-01-29

申请人： SK hynix Inc.

发明人： Seok-Jun LEE

IPC分类号： G06F3/06 ,  G06F12/02

摘要： A memory system includes a memory device including first memory blocks each including a memory cell storing a 1-bit data, and second memory blocks each including a memory cell storing a multi-bit data. The memory system further includes a controller configured to estimate data input/output speed of an operation requested by an external device and to determine, based on the estimated data input/output speed, a buffering ratio of pieces of buffered data, temporarily stored in the first memory blocks, to pieces of inputted data. The controller uses the buffer ratio to determine whether to program pieces of inputted data into the second memory blocks directly or to buffer the inputted data in the first memory blocks before programming it into the second memory blocks.

公开(公告)号：US20210056026A1

公开(公告)日：2021-02-25

申请号：US16845919

申请日：2020-04-10

申请人： SK hynix Inc.

发明人： Seok-Jun LEE

IPC分类号： G06F12/0811 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0873 ,  G06F12/02 ,  G06F12/14 ,  G06F9/4401 ,  G06F13/16

摘要： A memory system may include: a non-volatile memory device suitable for storing firmware; a volatile memory device comprising a write cache region for temporarily storing write data to be programmed into the non-volatile memory device and a firmware cache region for loading the firmware from the non-volatile memory device; and a controller suitable for: moving, to the write cache region, changeable firmware data that is generated or modified in the firmware cache region during an operation of the controller; programming the changeable firmware data, after it is moved into the write cache region, into the non-volatile memory device; and generating, in the firmware cache region, access information of the changeable firmware data.

公开(公告)号：US20210026633A1

公开(公告)日：2021-01-28

申请号：US16721117

申请日：2019-12-19

申请人： SK hynix Inc.

发明人： Seok-Jun LEE

IPC分类号： G06F9/30 ,  G06F12/123

摘要： Embodiments of the present invention disclosure relate to a memory system, a memory controller, and an operating method. With regard to a function group including all or some functions included in one of multiple binary codes stored in the memory device, a binary code including a first function that is executed at a first timepoint is loaded into a first memory area at a second timepoint that precedes the first time point, thereby minimizing the operation delay time of the memory system, and minimizing the overhead occurring in the processing of calling a specific function.