-
公开(公告)号：US11443805B2
公开(公告)日：2022-09-13
申请号：US17131456
申请日：2020-12-22
Applicant: SK hynix Inc.
Inventor： Sang Hyun Ban , Beom Seok Lee , Woo Tae Lee , Tae Hoon Kim , Hwan Jun Zang , Hye Jung Choi
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes word lines, bit lines intersecting the word lines, and memory cells coupled to and disposed between the word lines and the bit lines, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cells. In a reset operation, a memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is lower than a lowest threshold voltage among threshold voltages of the memory cells.
-
公开(公告)号：US11183634B2
公开(公告)日：2021-11-23
申请号：US16711286
申请日：2019-12-11
Applicant: SK hynix Inc.
Inventor： Woo Tae Lee , Beom Seok Lee
Abstract: A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.
-
Patent Agency Ranking
公开(公告)号：US20210110871A1
公开(公告)日：2021-04-15
申请号：US17131456
申请日：2020-12-22
Applicant: SK hynix Inc.
Inventor： Sang Hyun Ban , Beom Seok Lee , Woo Tae Lee , Tae Hoon Kim , Hwan Jun Zang , Hye Jung Choi
IPC: G11C13/00
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes word lines, bit lines intersecting the word lines, and memory cells coupled to and disposed between the word lines and the bit lines, each of the memory cells including a variable resistance layer in an amorphous state regardless of a value of data stored in the memory cells. In a reset operation, a memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is lower than a lowest threshold voltage among threshold voltages of the memory cells.
-
公开(公告)号：US20240015990A1
公开(公告)日：2024-01-11
申请号：US18299683
申请日：2023-04-12
Applicant: SK hynix Inc.
Inventor： Woo Tae Lee
Abstract: A semiconductor device may include: memory cells arranged in a first direction and a second direction intersecting the first direction; first capping patterns extending in the first direction and covering first sidewalls of the memory cells; second capping patterns extending in the second direction and covering second sidewalls of the memory cells; first gap-fill patterns each located between the second capping patterns adjacent in the first direction; second gap-fill patterns each located between the first gap-fill patterns adjacent in the second direction; and barrier layers each located between the second gap-fill patterns.
-
公开(公告)号：US11264095B2
公开(公告)日：2022-03-01
申请号：US17039480
申请日：2020-09-30
Applicant: SK hynix Inc.
Inventor： Sang Hyun Ban , Beom Seok Lee , Woo Tae Lee , Tae Hoon Kim , Hwan Jun Zang , Hye Jung Choi
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.
-
公开(公告)号：US11707005B2
公开(公告)日：2023-07-18
申请号：US16855760
申请日：2020-04-22
Applicant: SK hynix Inc.
Inventor： Gwang Sun Jung , Sang Hyun Ban , Jun Ku Ahn , Beom Seok Lee , Young Ho Lee , Woo Tae Lee , Jong Ho Lee , Hwan Jun Zang , Sung Lae Cho , Ye Cheon Cho , Uk Hwang
CPC classification number: H10N70/8825 , G11C13/003 , H10B63/24 , H10N70/841
Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.
-
公开(公告)号：US10825519B1
公开(公告)日：2020-11-03
申请号：US16687384
申请日：2019-11-18
Applicant: SK hynix Inc.
Inventor： Sang Hyun Ban , Beom Seok Lee , Woo Tae Lee , Tae Hoon Kim , Hwan Jun Zang , Hye Jung Choi
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.
-
-
-
-
-
-
Search Results
7
records
(took 0.014 seconds)
