公开(公告)号：US20210328579A1

公开(公告)日：2021-10-21

申请号：US17097943

申请日：2020-11-13

申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

发明人： Shin Hyun JEONG ,  Suhwan KIM ,  Gi Moon HONG ,  Ji Hyo KANG ,  Jae Hyeok YANG ,  Dae Han KWON ,  Dong Hyun KIM

IPC分类号： H03K3/012 ,  H03K3/037

摘要： A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

公开(公告)号：US20210096588A1

公开(公告)日：2021-04-01

申请号：US16889382

申请日：2020-06-01

申请人： SK hynix Inc.

发明人： Kyu Bong KONG ,  Jae Hyeok YANG ,  Gang Sik LEE

IPC分类号： G05F3/08

摘要： A semiconductor apparatus includes a voltage divider, a plurality of reference voltage controllers, and a plurality of receivers. The voltage divider outputs a plurality of division voltages. Each of the plurality of reference voltage controllers is configured to receive in common the plurality of division voltages. Each of the plurality of receivers is configured to receive data by utilizing at least one reference voltage. The plurality of reference voltage controllers are coupled to the plurality of receivers in a one-to-one manner, and each of the plurality of reference voltage controllers is configured to select at least one division voltage among the plurality of division voltages and provide the one division voltage as the at least one reference voltage to a corresponding receiver among the plurality of receivers.

公开(公告)号：US20220155814A1

公开(公告)日：2022-05-19

申请号：US17226952

申请日：2021-04-09

申请人： SK hynix Inc.

发明人： Ji Hyo KANG ,  Kyung Hoon KIM ,  Jae Hyeok YANG ,  Sang Yeon BYEON ,  Gang Sik LEE ,  Joo Hyung CHAE

IPC分类号： G06F1/10 ,  H03K19/096

摘要： Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.