公开(公告)号：US20210328579A1

公开(公告)日：2021-10-21

申请号：US17097943

申请日：2020-11-13

申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

发明人： Shin Hyun JEONG ,  Suhwan KIM ,  Gi Moon HONG ,  Ji Hyo KANG ,  Jae Hyeok YANG ,  Dae Han KWON ,  Dong Hyun KIM

IPC分类号： H03K3/012 ,  H03K3/037

摘要： A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

公开(公告)号：US20240356550A1

公开(公告)日：2024-10-24

申请号：US18495592

申请日：2023-10-26

申请人： SK hynix Inc.

发明人： Ji Hyo KANG

IPC分类号： H03K19/017 ,  G11C7/10

CPC分类号： H03K19/01742 ,  G11C7/1057 ,  G11C7/1084

摘要： A buffer circuit includes a driving control circuit and a driving circuit. The driving control circuit changes a voltage level of an input signal to generate a pull-up control signal and a pull-down control signal. The pull-up control signal has a voltage level lower than a high boundary voltage level of the input signal. The pull-down control signal has a voltage level higher than a low boundary voltage level of the input signal. The driving circuit generates an output signal based on the pull-up control signal and the pull-down control signal.

公开(公告)号：US20220190829A1

公开(公告)日：2022-06-16

申请号：US17322533

申请日：2021-05-17

申请人： SK hynix Inc.

发明人： Ji Hyo KANG

IPC分类号： H03K19/0175 ,  H03K19/003

摘要： A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

公开(公告)号：US20220085811A1

公开(公告)日：2022-03-17

申请号：US17170532

申请日：2021-02-08

申请人： SK hynix Inc.

发明人： Ji Hyo KANG

IPC分类号： H03K19/0185

摘要： A signal transmission circuit of a semiconductor device includes a first emphasis circuit and a second emphasis circuit. The first emphasis circuit feeds a signal of an output node back to an input node. The first emphasis circuit may perform a first emphasis operation on a signal of the input node and the signal of the output node by adjusting a feedback time of the first emphasis circuit. The second emphasis circuit may be connected in parallel with the first emphasis circuit to perform a feedback of the signal of the output node to the input node. The second emphasis circuit may perform a second emphasis operation on the signal of the input node and the signal of the output node by adjusting a feedback time of the second emphasis circuit.

公开(公告)号：US20240348251A1

公开(公告)日：2024-10-17

申请号：US18498852

申请日：2023-10-31

申请人： SK hynix Inc.

发明人： Ji Hyo KANG ,  Hyun Bae LEE

IPC分类号： H03K19/00 ,  H03K17/687

CPC分类号： H03K19/0005 ,  H03K17/6877

摘要： A buffer circuit may include a buffer unit including a first resistor connected between a power source terminal and a first node, a first inductor set connected between the first node and a first input terminal, a second resistor connected between the power source terminal and a second node, and a second inductor set connected between the second node and a second input terminal, and a first variable capacitance circuit connected between the first node and the second node, and configured to adjust a first capacitance value according to a plurality of first adjustment signals.

公开(公告)号：US20230170905A1

公开(公告)日：2023-06-01

申请号：US18096866

申请日：2023-01-13

申请人： SK hynix Inc.

发明人： Ji Hyo KANG

IPC分类号： H03K19/0175 ,  H03K19/003

CPC分类号： H03K19/017509 ,  H03K19/003

摘要： A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

公开(公告)号：US20210359686A1

公开(公告)日：2021-11-18

申请号：US17034796

申请日：2020-09-28

申请人： SK hynix Inc.

发明人： Ji Hyo KANG

IPC分类号： H03K19/096 ,  H03K19/17784 ,  H03K19/0185 ,  H03K3/356

摘要： A clocked latch circuit includes an amplification circuit, a latch circuit, a first current source, and a second current source. The amplification circuit changes voltage levels of first and second output signals based on a clock signal, a first input signal, and a second input signal. The latch circuit maintains the voltage levels of the first and second output signals based on a complementary signal of the clock signal. The first current source allows a first current to flow to activate the amplification circuit. The second current source allows a second current that is different from the first current to flow to activate the latch circuit.

公开(公告)号：US20200294556A1

公开(公告)日：2020-09-17

申请号：US16890158

申请日：2020-06-02

申请人： SK hynix Inc.

发明人： Ji Hyo KANG

IPC分类号： G11C5/14 ,  G11C11/40 ,  G11C7/10 ,  G11C7/14 ,  G11C8/10

摘要： A semiconductor apparatus includes a reference voltage generating circuit and a buffer. The reference voltage generating circuit may generate, based on a voltage setting signal, a first reference voltage and a second reference voltage, which has the same level as the first reference voltage or has a lower level than the first reference voltage by an amount of a unit level. The buffer may generate an output signal based on the first reference voltage, the second reference voltage and an input signal.

公开(公告)号：US20240340010A1

公开(公告)日：2024-10-10

申请号：US18657141

申请日：2024-05-07

申请人： SK hynix Inc.

发明人： Ji Hyo KANG ,  Kyung Hoon KIM

IPC分类号： H03K19/0185 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  H03K17/687

CPC分类号： H03K19/018521 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  H03K17/6872

摘要： A semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. The clock distribution network receives a system clock signal and drives the system clock signal to a CMOS level and a CML level to signal in different manners. The data output circuit outputs data based on the clock signal driven to the CMOS level. The data input circuit receives data based on the clock signal driven to the CML level.

公开(公告)号：US20240312502A1

公开(公告)日：2024-09-19

申请号：US18497747

申请日：2023-10-30

申请人： SK hynix Inc.

发明人： Ji Hyo KANG

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/1039 ,  G11C7/1057

摘要： A clock distribution network includes at least two buffers that receive the same clock signal and generate different clock signals. In a first operation mode, the at least two buffers are all activated. In a second operation mode, one of the at least two buffers is activated. In the second operation mode, the other one of the at least two buffers is partially activated without being deactivated.