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公开(公告)号：US11652474B2
公开(公告)日：2023-05-16
申请号：US17316329
申请日：2021-05-10
发明人： Soyeong Shin , Yongjae Lee , Jiheon Park , Deog-Kyoon Jeong
CPC分类号： H03K5/135 , H03K2005/00019
摘要： A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.
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2.发明授权公开(公告)号：US11936386B2
公开(公告)日：2024-03-19
申请号：US18298297
申请日：2023-04-10
发明人： Soyeong Shin , Yongjae Lee , Jiheon Park , Deog-Kyoon Jeong
CPC分类号： H03K5/135 , H03K2005/00019
摘要： A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.
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公开(公告)号：US11121716B2
公开(公告)日：2021-09-14
申请号：US17027570
申请日：2020-09-21
发明人： Soyeong Shin , Han-Gon Ko , Deog-Kyoon Jeong
摘要： A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.
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公开(公告)号：US11283655B2
公开(公告)日：2022-03-22
申请号：US17174960
申请日：2021-02-12
发明人： Deog-Kyoon Jeong , KwangHoon Lee , Jung Hun Park , Han-Gon Ko , Soyeong Shin
摘要： Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver (20) generating waveform including data to be transmitted; and an FFE driver block (40) connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.
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