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5 条记录 (耗时 0.018 秒)

    Injection locked phase locked loop
    1.
    发明授权
    Injection locked phase locked loop 有权

    公开(公告)号：US10044359B1

    公开(公告)日：2018-08-07

    申请号：US15701333

    申请日：2017-09-11

    申请人： SK hynix Inc. ,  Seoul National University R&DB FOUNDATION

    发明人： Sungwoo Kim ,  Han-Gon Ko ,  Suhwan Kim ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/099 ,  H03L7/091 ,  H03L7/18

    摘要： An injection locked phase locked loop includes an injection locked oscillator configured to generate an oscillation signal according to an injection signal and to generate a replica signal by replicating the oscillation signal when the injection signal is deactivated; a phase controller configured to generate a phase control signal according to a phase error signal; and an error detector configured to generate the phase error signal by comparing a phase of the oscillation signal and a phase of the replica signal, and to control a phase difference between the oscillation signal and the replica signal according to the phase control signal.

    Integrated circuit and memory
    2.
    发明授权
    Integrated circuit and memory 有权

    公开(公告)号：US11423963B2

    公开(公告)日：2022-08-23

    申请号：US16686941

    申请日：2019-11-18

    申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

    发明人： Deog-Kyoon Jeong ,  Han-Gon Ko ,  Chan-Ho Kye ,  So-Yeong Shin

    IPC分类号： G11C7/22 ,  G11C7/10 ,  H03L7/081 ,  H03L7/197

    摘要： An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.

    Semiconductor device for adjusting phases of multi-phase signals
    3.
    发明授权
    Semiconductor device for adjusting phases of multi-phase signals 有权

    公开(公告)号：US11121716B2

    公开(公告)日：2021-09-14

    申请号：US17027570

    申请日：2020-09-21

    申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

    发明人： Soyeong Shin ,  Han-Gon Ko ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/081 ,  H03K5/131 ,  G06F1/10 ,  H03K5/00

    摘要： A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.