公开(公告)号：US20220329235A1

公开(公告)日：2022-10-13

申请号：US17850385

申请日：2022-06-27

Applicant: SOCIONEXT INC.

Inventor： Koshiro DATE

IPC: H03K3/037 ,  G06F30/392

Abstract: A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.

公开(公告)号：US20250157929A1

公开(公告)日：2025-05-15

申请号：US19022581

申请日：2025-01-15

Applicant: SOCIONEXT INC.

Inventor： Koshiro DATE

IPC: H01L23/528 ,  H10D30/67 ,  H10D62/10 ,  H10D84/85

Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.

公开(公告)号：US20210320065A1

公开(公告)日：2021-10-14

申请号：US17357211

申请日：2021-06-24

Applicant: SOCIONEXT INC.

Inventor： Koshiro DATE

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.