公开(公告)号：US09921983B2

公开(公告)日：2018-03-20

申请号：US14469981

申请日：2014-08-27

Applicant: SOCIONEXT INC.

Inventor： Takashi Okuda ,  Satoru Okamoto

IPC: G06F13/28 ,  G06F13/30

CPC classification number: G06F13/30 ,  G06F13/28 ,  Y02D10/14

Abstract: Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation.