公开(公告)号：US09921983B2

公开(公告)日：2018-03-20

申请号：US14469981

申请日：2014-08-27

Applicant: SOCIONEXT INC.

Inventor： Takashi Okuda ,  Satoru Okamoto

IPC: G06F13/28 ,  G06F13/30

CPC classification number: G06F13/30 ,  G06F13/28 ,  Y02D10/14

Abstract: Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation.

公开(公告)号：US20210011873A1

公开(公告)日：2021-01-14

申请号：US17037431

申请日：2020-09-29

Applicant: SOCIONEXT INC.

Inventor： Eiichi Nimoda ,  Seiji Goto ,  Satoru Okamoto ,  Shuichi Yamane ,  Yasuo Nishiguchi

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F12/10

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.

公开(公告)号：US10853287B2

公开(公告)日：2020-12-01

申请号：US16392240

申请日：2019-04-23

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Eiichi Nimoda ,  Satoru Okamoto

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/38

Abstract: Processing by an information processing system is speeded up. A first semiconductor integrated circuit designates a first address of a memory connected to a second semiconductor integrated circuit that is a data transmission destination, based on first memory map information in which addresses of memories respectively used by the semiconductor integrated circuits are defined, converts the first address to a second address of the memory defined in second memory map information referred to by the data transmission destination, and outputs the second address and transmission data by using a PCIe interface. A switch transfers the second address and the transmission data to the data transmission destination by using PCIe interfaces. The data transmission destination receives the second address and the transmission data by using a PCIe interface and writes the transmission data into the reception buffer region of the memory corresponding to the second address.

公开(公告)号：US11003611B2

公开(公告)日：2021-05-11

申请号：US17037431

申请日：2020-09-29

Applicant: SOCIONEXT INC.

Inventor： Eiichi Nimoda ,  Seiji Goto ,  Satoru Okamoto ,  Shuichi Yamane ,  Yasuo Nishiguchi

IPC: G06F12/02 ,  G06F13/40 ,  G06F12/10 ,  G06F13/16 ,  G06F13/42

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.