公开(公告)号：US11621259B2

公开(公告)日：2023-04-04

申请号：US17233177

申请日：2021-04-16

Applicant: SOCIONEXT INC.

Inventor： Toshihiro Nakamura ,  Taro Fukunaga

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.

公开(公告)号：US10825760B2

公开(公告)日：2020-11-03

申请号：US16165486

申请日：2018-10-19

Applicant: SOCIONEXT INC.

Inventor： Toshihiro Nakamura ,  Isao Motegi ,  Noriyuki Shimazu ,  Masanobu Hirose ,  Taro Fukunaga

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.