公开(公告)号：US10825760B2

公开(公告)日：2020-11-03

申请号：US16165486

申请日：2018-10-19

Applicant: SOCIONEXT INC.

Inventor： Toshihiro Nakamura ,  Isao Motegi ,  Noriyuki Shimazu ,  Masanobu Hirose ,  Taro Fukunaga

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

公开(公告)号：US20200243128A1

公开(公告)日：2020-07-30

申请号：US16847551

申请日：2020-04-13

Applicant: Socionext Inc.

Inventor： Masataka Sato ,  Hideo Akiyoshi ,  Masanobu Hirose ,  Yoshinobu Yamagami

IPC: G11C11/408 ,  G11C11/4099 ,  G11C5/02

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

公开(公告)号：US12213298B2

公开(公告)日：2025-01-28

申请号：US17556910

申请日：2021-12-20

Applicant: SOCIONEXT INC.

Inventor： Masanobu Hirose

IPC: H10B10/00 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L29/06 ,  H01L29/423

Abstract: Transistors (N3, N4) corresponding to a drive transistor (PD1), transistors (N5, N6) corresponding to a drive transistor (PD2), transistors (N7, N8) corresponding to an access transistor (PG1), and transistors (N1, N2) corresponding to an access transistor (PG2) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. Further, the transistors (P1, P2) overlap the transistors (N3, N6) in plan view.

公开(公告)号：US11915744B2

公开(公告)日：2024-02-27

申请号：US17556268

申请日：2021-12-20

Applicant: Socionext Inc.

Inventor： Masanobu Hirose

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H10B10/12 ,  H10B10/125

Abstract: Transistors (N1 to N12) corresponding to drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. The transistors (P1, P2) overlap the transistors (N3, N8), respectively, in plan view.

公开(公告)号：US10685685B2

公开(公告)日：2020-06-16

申请号：US16574989

申请日：2019-09-18

Applicant: SOCIONEXT INC.

Inventor： Masanobu Hirose

IPC: G11C5/14 ,  H03K17/56

Abstract: In a semiconductor integrated circuit employing power gating, a control input signal is propagated to one or more first power switches through a first propagation path and to one or more second power switches through a second propagation path. A restoration determination circuit receives a first signal of the first propagation path and a second signal of the second propagation path and generates a control output signal. When the control signal performs restoration transition, the restoration determination circuit causes the control output signal to perform the restoration transition in accordance with a later timing of timings of restoration transitions of the first and second signals.

公开(公告)号：US12232308B2

公开(公告)日：2025-02-18

申请号：US17840079

申请日：2022-06-14

Applicant: Socionext Inc.

Inventor： Masanobu Hirose

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Nanosheets 21a to 21d are formed in line in this order in the X direction, and nanosheets 21e to 21h are formed in line in this order in the X direction. Faces of the nanosheets 21c, 21f, and 21g on the first side as one of the opposite sides in the X direction are exposed from gate interconnects 31c, 31e, and 31f, respectively. Faces of the nanosheets 21a, 21b, 21d, 21e, and 21h on the second side as the other side in the X direction are exposed from gate interconnects 31a to 31d and 31g, respectively.

公开(公告)号：US11251125B2

公开(公告)日：2022-02-15

申请号：US17071812

申请日：2020-10-15

Applicant: SOCIONEXT INC.

Inventor： Masanobu Hirose ,  Toshihiro Nakamura

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/50

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects provided in I/O cell rows are connected to a power supply interconnect provided between the I/O cell rows via power supply interconnects. The power supply interconnect is thicker than the in-row power supply interconnects.

公开(公告)号：US10943643B2

公开(公告)日：2021-03-09

申请号：US16847551

申请日：2020-04-13

Applicant: SOCIONEXT INC.

Inventor： Masataka Sato ,  Hideo Akiyoshi ,  Masanobu Hirose ,  Yoshinobu Yamagami

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4099

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

公开(公告)号：US10153264B2

公开(公告)日：2018-12-11

申请号：US15653084

申请日：2017-07-18

Applicant: SOCIONEXT INC.

Inventor： Masanobu Hirose

IPC: H01L27/02 ,  G11C11/418 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an SRAM cell including fin-type transistors. The SRAM cell is defined by transistors each of which has a fin structure and by a local metal interconnection layer. Bit lines are formed on the local metal interconnection layer, and diffusion layer contacts corresponding to bit line nodes are connected through vias to the bit lines.

公开(公告)号：US12048134B2

公开(公告)日：2024-07-23

申请号：US17879415

申请日：2022-08-02

Applicant: Socionext Inc.

Inventor： Masanobu Hirose ,  Yasunori Murase

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H10B10/18

Abstract: Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.