公开(公告)号：US12119339B2

公开(公告)日：2024-10-15

申请号：US18423159

申请日：2024-01-25

Applicant: SOCIONEXT INC.

Inventor： Yoko Shiraki

IPC: H01L27/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/775

Abstract: A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.

公开(公告)号：US11916057B2

公开(公告)日：2024-02-27

申请号：US17245509

申请日：2021-04-30

Applicant: SOCIONEXT INC.

Inventor： Yoko Shiraki

IPC: H01L23/00 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/092 ,  H01L29/00 ,  H01L29/06 ,  H01L29/775

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/775

Abstract: A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.