公开(公告)号：US11782393B2

公开(公告)日：2023-10-10

申请号：US17998519

申请日：2021-06-02

Applicant: SOCPRA SCIENCES ET GENIE S.E.C.

Inventor： Frédéric Nolet ,  Nicolas Roy ,  Jean-François Pratte ,  Frederik Dubois

IPC: G04F10/00 ,  H03K5/01 ,  H03K3/03 ,  H03K5/00

CPC classification number: G04F10/005 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

Abstract: Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurements using a third oscillator for the second Vernier process has significant advantages compared to changing the period of the second oscillator during the measurement cycle. The Vernier architecture described herein may operate with faster oscillators, reducing the number of intervals before converging and leading to a lower time conversion and a better timing jitter Adding multiple cascaded Vernier interpolation may further improve the TDC measurement resolution while having only a small increment of time required to resolve the time interval calculations.