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公开(公告)号：US12123948B2
公开(公告)日：2024-10-22
申请号：US17089403
申请日：2020-11-04
Applicant: HYUNDAI MOBIS CO., LTD.
Inventor： Young Kyun Kim
CPC classification number: G01S17/08 , G04F10/005
Abstract: A LiDAR sensor having a parameter optimization function may include: a laser diode configured to emit a laser light signal; a photo diode configured to receive a maximum laser light reflection signal reflected from a target object at a scannable maximum distance in the laser light signal; and a parameter setting unit configured to set a parameter related to an output intensity of the laser light signal or a reception intensity of the laser light signal based on the maximum laser light reflection signal.
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公开(公告)号：US12088307B2
公开(公告)日：2024-09-10
申请号：US18356218
申请日：2023-07-21
Inventor： Mao-Ruei Li , Ming Hsien Tsai , Ruey-Bin Sheen
IPC: H03K7/08 , G04F10/00 , G04F10/04 , G06F30/20 , G06F30/337 , G11C16/32 , H03K3/017 , H03K5/156 , H03L7/06 , H03L7/085
CPC classification number: H03K7/08 , G04F10/005 , G04F10/04 , G06F30/20 , G06F30/337 , G11C16/32 , H03K3/017 , H03K5/1565 , H03L7/06 , H03L7/085
Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.
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公开(公告)号：US20240272589A1
公开(公告)日：2024-08-15
申请号：US18429541
申请日：2024-02-01
Applicant: ROHM CO., LTD.
Inventor： Keno SATO , Tamotsu ICHIKAWA , Takashi ISHIDA , Toshiyuki OKAMOTO , Takayuki NAKATANI , Haruo KOBAYASHI
CPC classification number: G04F10/005 , H03M1/0604
Abstract: A time-to-digital converter circuit that measures a time difference between a first input signal and a second input signal includes: a jitter superimposition circuit that superimposes a jitter, which changes temporally, on one of the first input signal and the second input signal to generate a first intermediate signal and a second intermediate signal; a time-to-digital converter that measures a time difference between the first intermediate signal and the second intermediate signal each time the jitter changes; and a statistical processor that statistically processes a plurality of time differences measured by the time-to-digital converter in response to a plurality of jitters, and calculates a time difference between the first input signal and the second input signal.
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公开(公告)号：US12063049B2
公开(公告)日：2024-08-13
申请号：US17683916
申请日：2022-03-01
Applicant: Anokiwave, Inc.
Inventor： Eythan Familier , Kartik Sridharan , Jun Li , Gaurav Menon , Shamsun Nahar , Akhil Garlapati , Scott Humphreys , Antonio Geremia
CPC classification number: H03M1/1028 , G04F10/005 , H03L7/1976
Abstract: Digital post-processing of time-to-digital converter (TDC) output data can be used to map each TDC code to the ideal one, but this requires knowing the TDC input-output mapping. Therefore, a calibration system and method are provided for characterizing operation of a TDC to compensate for non-idealities. Input signals having a known time difference are provided to the TDC, and a mapping between the TDC output and the known time difference is stored in a mapping table. With the described method, it is possible to input an input ramp of very low slope to construct this mapping to a desired resolution during a background calibration procedure. This characterizing and mapping can be performed across a range of input signals having different known time differences. After calibration, a mapping table can be used by a mapping circuit of the TDC or by a digital post-processing function to provide a compensated TDC output.
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公开(公告)号：US12038725B2
公开(公告)日：2024-07-16
申请号：US17021973
申请日：2020-09-15
Applicant: Intel Corporation
Inventor： Zheng Gu
CPC classification number: G04F10/005 , H03L7/085 , H03M1/0602
Abstract: A bipolar TDC apparatus with a phase detection and signal switching circuitry and a phase error measurement circuitry. The phase detection and signal switching circuitry include a multiplexer and phase detector, together referred to as PD_MUX. The PD_MUX is used to handle the order of the two input signal phases of a TDC, or in other words, to enable TDC the bipolarity detection of the phase error. The apparatus detects first the polarity of the phase error and then prepares the right phase order when they arrive at the TDC measurement elements of the phase error measurement circuitry to ensure that always the earlier one starts the TDC and the later one triggers the measurement event. As such, the phase measurement circuitry (or measurement block) provides the phase error magnitude information, while the PD_MUX provides the sign—polarity information.
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Patent Agency Ranking
公开(公告)号：US20240231283A1
公开(公告)日：2024-07-11
申请号：US18518517
申请日：2023-11-23
Applicant: Seer Microelectronics, Inc.
Inventor： Ming-Ching Kuo , Ming-Feng Huang
IPC: G04F10/00
CPC classification number: G04F10/005
Abstract: The present invention relates a multi-shot time-to-digital converter and a time-measurement device. The multi-shot time-to-digital converter includes a time-to-digital conversion circuit and a timing control circuit. The timing control circuit is coupled to the time-to-digital conversion circuit and sending a start signal to the time-to-digital conversion circuit multiple times for measuring a time interval corresponding to the start signal. The time-to-digital conversion circuit obtains a fine phase time based on a plurality of clock signals to measure the time interval and provides a plurality of time-to-digital codes for digital processing. The clock signals have different phases. The time-to-digital codes are further processed to obtain the time-to-digital codes with better resolution.
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公开(公告)号：US20240231281A1
公开(公告)日：2024-07-11
申请号：US18152747
申请日：2023-01-10
Applicant: NANYA TECHNOLOGY CORPORATION
Inventor： Heng Lin
IPC: G04F10/00
CPC classification number: G04F10/005
Abstract: A time-to-digital converter apparatus and a converting method thereof are provided. An output signal of a first ring oscillator circuit is counted to generate a first digital code. An output signal of a second ring oscillator circuit is counted to generate a second digital code. A corresponding third digital code is generated according to a time point of phase coincidence between one of outputs of a plurality of first delay stages of the first ring oscillator circuit and one of outputs of a plurality of second delay stages of the second ring oscillator circuit.
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公开(公告)号：US12021959B2
公开(公告)日：2024-06-25
申请号：US17731651
申请日：2022-04-28
Applicant: Mellanox Technologies, Ltd.
Inventor： Igal Kushnir
CPC classification number: H04L7/0016 , G04F10/005 , H03K3/017
Abstract: A system includes a first device, coupled to a link, which transmits a signal having a repeating pattern on one or more paths of the link. The system includes a second device coupled to the link and including one or more circuits and a time-to-digital converter (TDC). The second device is to receive at the one or more circuits the signal. The second device is to determine, by the TDC, a current duty cycle of the signal, the current duty cycle having a first duration associated with a first portion of the signal and a second duration associated with a second portion of the signal. The second device is further to determine the current duty cycle fails to satisfy a condition associated with a target duty cycle in response to determining the current duty cycle of the signal and adjust the current duty cycle to obtain an adjusted duty cycle.
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公开(公告)号：US12015411B2
公开(公告)日：2024-06-18
申请号：US17752774
申请日：2022-05-24
Applicant: Synopsys, Inc.
Inventor： Emil Gizdarski , Anubhav Sinha
CPC classification number: H03K5/131 , G04F10/005 , H03K2005/00058
Abstract: A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.
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公开(公告)号：US20240168442A1
公开(公告)日：2024-05-23
申请号：US17989045
申请日：2022-11-17
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Ajay Bharadwaj , Romesh Kumar Nandwana
CPC classification number: G04F10/005 , H03L7/0992
Abstract: A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.
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