公开(公告)号：US09251871B2

公开(公告)日：2016-02-02

申请号：US14358193

申请日：2012-11-14

Applicant: SOITEC

Inventor： Richard Ferrant ,  Joerg Vollrath ,  Roland Thewes ,  Wolfgang Hoenlein ,  Hofmann Franz ,  Gerhard Enders

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract translation: 本发明涉及用于感测和放大存储在存储单元中的数据的读出放大器，该读出放大器连接在位线（BL）和与第一位线的基准位线互补（/ BL）之间，并且包括：感测 电路（SC）能够提供指示存储在存储单元中的数据的输出; 以及预充电和解码电路（PDC），包括一对双栅极晶体管（T5，T6），用于在预充电操作期间对第一和第二位线进行预充电，并将由感测电路提供的输出传送到数据线（LIO， / LIO）。

公开(公告)号：US20140321225A1

公开(公告)日：2014-10-30

申请号：US14358193

申请日：2012-11-14

Applicant: SOITEC

Inventor： Richard Ferrant ,  Joerg Vollrath ,  Roland Thewes ,  Wolfgang Hoenlein ,  Hofmann Franz ,  Gerhard Enders

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract translation: 本发明涉及用于感测和放大存储在存储单元中的数据的读出放大器，该读出放大器连接在位线（BL）和与第一位线的基准位线互补（/ BL）之间，并且包括：感测 电路（SC）能够提供指示存储在存储单元中的数据的输出; 以及预充电和解码电路（PDC），包括一对双栅极晶体管（T5，T6），用于在预充电操作期间对第一和第二位线进行预充电，并将由感测电路提供的输出传送到数据线（LIO， / LIO）。