公开(公告)号：US09576642B2

公开(公告)日：2017-02-21

申请号：US14785955

申请日：2014-04-24

Applicant: Soitec

Inventor： Roland Thewes ,  Richard Ferrant

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/18 ,  G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/14 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/04 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4099

Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array,—at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Abstract translation: 本发明涉及一种半导体存储器件，包括：至少一个读出放大器电路，用于读取从存储器阵列中的选定存储单元感测的数据，至少一个参考电路，每个参考电路是读出放大器电路的复制品，并具有输出 参考电路通过其输出输出物理量;调节网络，向每个读出放大器电路和每个参考电路提供调节信号，其中调节信号是根据输出物理量随时间和/或空间的平均得出的，其中 调节网络包括：控制单元，被配置为将参考电路的每个输出的物理量与目标平均值相加，所述控制单元基于所述和传送调节信号，所述调节信号馈送到每个常规读出放大器 电路和每个参考电路。

公开(公告)号：US09478275B2

公开(公告)日：2016-10-25

申请号：US14434579

申请日：2013-10-10

Applicant: Soitec

Inventor： Roland Thewes

IPC: G11C7/02 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C5/146 ,  G11C7/065

Abstract: The disclosure relates to semiconductor memory devices and related methods. A semiconductor memory device comprises: a single-ended sense amplifier circuit for reading data sensed from selected memory cells in a memory array, the sense amplifier having a first node used to feed in a reference signal, a second node coupled to a bit line, and sense transistors responsible for amplifying the content of a selected memory cell during a sense operation, a reference circuit having replica transistors of the sense transistors and further comprising a regulation network designed so that each replica transistor operates in a stable operating point, and wherein the regulation network generates a control voltage that is applied to the sense amplifier circuit.

Abstract translation: 本公开涉及半导体存储器件及相关方法。 半导体存储器件包括：单端读出放大器电路，用于读取从存储器阵列中的选定存储单元感测的数据，读出放大器具有用于馈送参考信号的第一节点，耦合到位线的第二节点， 以及感测晶体管，其负责在感测操作期间放大所选择的存储单元的内容;参考电路，其具有所述感测晶体管的复制晶体管，并且还包括设计成使得每个复制晶体管在稳定工作点工作的调节网络，并且其中 调节网络产生施加到读出放大器电路的控制电压。

公开(公告)号：US20140376318A1

公开(公告)日：2014-12-25

申请号：US14372345

申请日：2013-01-16

Applicant: SOITEC

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/08 ,  G11C11/4091 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

Abstract: a circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.

Abstract translation: 用于检测包括与第一信号线互补的第一信号线和第二信号线的一对双信号线上的电压差的电路，包括：布置在第一和第二信号线之间的一对交叉耦合反相器 每个反相器具有上拉晶体管和下拉晶体管，上拉晶体管或下拉晶体管的源极分别连接到第一和第二拉电压信号，解码晶体管具有源极和漏极 分别耦合到第一和第二信号线之一的端子和由解码控制信号控制的门，由此当解码晶体管被解码控制信号导通时，在第一和第二信号线之间建立短路通过 该电流从第一和第二拉电压信号之一流动，从而在第一和第二拉电压信号之间产生干扰。

公开(公告)号：US20140321225A1

公开(公告)日：2014-10-30

申请号：US14358193

申请日：2012-11-14

Applicant: SOITEC

Inventor： Richard Ferrant ,  Joerg Vollrath ,  Roland Thewes ,  Wolfgang Hoenlein ,  Hofmann Franz ,  Gerhard Enders

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract translation: 本发明涉及用于感测和放大存储在存储单元中的数据的读出放大器，该读出放大器连接在位线（BL）和与第一位线的基准位线互补（/ BL）之间，并且包括：感测 电路（SC）能够提供指示存储在存储单元中的数据的输出; 以及预充电和解码电路（PDC），包括一对双栅极晶体管（T5，T6），用于在预充电操作期间对第一和第二位线进行预充电，并将由感测电路提供的输出传送到数据线（LIO， / LIO）。

公开(公告)号：US09390771B2

公开(公告)日：2016-07-12

申请号：US14372345

申请日：2013-01-16

Applicant: SOITEC

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

Abstract: A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, a decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.

Abstract translation: 一种用于感测一对双信号线上的电压差的电路，包括与第一信号线互补的第一信号线和第二信号线，包括：一对交叉耦合的反相器，布置在第一和第二信号线之间 每个反相器具有上拉晶体管和下拉晶体管，上拉晶体管或下拉晶体管的源极分别连接到第一和第二拉电压信号，解码晶体管具有源极和 分别耦合到第一和第二信号线之一的漏极端子和由解码控制信号控制的栅极，由此当解码晶体管由解码控制信号导通时，在第一和第二信号线之间建立短路 电流从第一和第二拉电压信号之一流过，从而在第一和第二拉电压信号之间产生干扰。

公开(公告)号：US20160086652A1

公开(公告)日：2016-03-24

申请号：US14785955

申请日：2014-04-24

Applicant: SOITEC

Inventor： Roland Thewes ,  Richard Ferrant

IPC: G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/04 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4099

Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array, at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Abstract translation: 本发明涉及一种半导体存储器件，包括：至少一个读出放大器电路，用于读取从存储器阵列中的选定存储单元感测的数据，至少一个参考电路，每个参考电路是读出放大器电路的复制品， 所述参考电路提供输出物理量;调节网络，向每个读出放大器电路和每个参考电路提供调节信号，其中调节信号是根据输出物理量随时间和/或空间的平均得出的，其中， 调节网络包括：控制单元，被配置为将参考电路的每个输出的物理量与目标平均值相加，所述控制单元基于所述和传送调节信号，所述调节信号馈送到每个常规读出放大器电路 和每个参考电路。

公开(公告)号：US09251871B2

公开(公告)日：2016-02-02

申请号：US14358193

申请日：2012-11-14

Applicant: SOITEC

Inventor： Richard Ferrant ,  Joerg Vollrath ,  Roland Thewes ,  Wolfgang Hoenlein ,  Hofmann Franz ,  Gerhard Enders

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract translation: 本发明涉及用于感测和放大存储在存储单元中的数据的读出放大器，该读出放大器连接在位线（BL）和与第一位线的基准位线互补（/ BL）之间，并且包括：感测 电路（SC）能够提供指示存储在存储单元中的数据的输出; 以及预充电和解码电路（PDC），包括一对双栅极晶体管（T5，T6），用于在预充电操作期间对第一和第二位线进行预充电，并将由感测电路提供的输出传送到数据线（LIO， / LIO）。

公开(公告)号：US20150279448A1

公开(公告)日：2015-10-01

申请号：US14434579

申请日：2013-10-10

Applicant: Soitec

Inventor： Roland Thewes

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  G11C5/146 ,  G11C7/065

Abstract: The disclosure relates to semiconductor memory devices and related methods. A semiconductor memory device comprises: a single-ended sense amplifier circuit for reading data sensed from selected memory cells in a memory array, the sense amplifier having a first node used to feed in a reference signal, a second node coupled to a bit line, and sense transistors responsible for amplifying the content of a selected memory cell during a sense operation, a reference circuit having replica transistors of the sense transistors and further comprising a regulation network designed so that each replica transistor operates in a stable operating point, and wherein the regulation network generates a control voltage that is applied to the sense amplifier circuit.

Abstract translation: 本公开涉及半导体存储器件及相关方法。 半导体存储器件包括：单端读出放大器电路，用于读取从存储器阵列中的选定存储单元感测的数据，读出放大器具有用于馈送参考信号的第一节点，耦合到位线的第二节点， 以及感测晶体管，其负责在感测操作期间放大所选择的存储单元的内容;参考电路，其具有所述感测晶体管的复制晶体管，并且还包括设计成使得每个复制晶体管在稳定工作点工作的调节网络，并且其中 调节网络产生施加到读出放大器电路的控制电压。