METHOD FOR TRANSFERRING A USEFUL LAYER TO A FRONT FACE OF CARRIER SUBSTRATE

    公开(公告)号:US20240357937A1

    公开(公告)日:2024-10-24

    申请号:US18685991

    申请日:2022-08-17

    申请人: Soitec

    IPC分类号: H10N30/072 H10N30/853

    摘要: A method for transferring a useful layer to a carrier substrate comprises: a) providing a donor substrate including a donor layer; b) forming an embrittlement area by implanting species in the donor layer and defining therewith a useful layer; c) assembling the carrier substrate with the donor substrate; d) a heat treatment step including a first phase and a second phase, wherein the first phase, having a first duration, is heated to a first temperature and is suitable for maturing defects and preventing a fracture from occurring in the embrittlement area, and wherein the second phase, having a second duration, comprises a bearing at a second temperature, below the first temperature, and is suitable for causing a fracture to occur along the embrittlement area.

    HOLDING DEVICE ARRANGEMENT FOR USE IN AN IMPLANTATION PROCESS OF A PIEZOELECTRIC SUBSTRATE

    公开(公告)号:US20240297011A1

    公开(公告)日:2024-09-05

    申请号:US18575538

    申请日:2022-07-19

    申请人: Soitec

    摘要: A holding device arrangement for use in an implantation process of a piezoelectric substrate comprises a substrate holding device with an elastic and thermo-conductive layer for receiving a piezoelectric substrate, and means for electrically connecting the surface of the elastic and thermo-conductive layer for receiving the piezoelectric substrate to ground potential. A method for implanting a piezoelectric substrate is performed using such holding device arrangement as described above, and an ion implanter may include such a holding device arrangement.

    NCFET TRANSISTOR COMPRISING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE

    公开(公告)号:US20240170577A1

    公开(公告)日:2024-05-23

    申请号:US18551104

    申请日:2022-03-17

    申请人: Soitec

    IPC分类号: H01L29/786 H01L21/762

    CPC分类号: H01L29/78603 H01L21/76254

    摘要: An NCFET transistor comprises a semiconductor-on-insulator substrate for a field-effect transistor, and the NCFET transistor successively comprises, from its base to its surface: a semiconductor carrier substrate; a single ferroelectric layer, arranged in direct contact with the carrier substrate, which layer is designed to be biased so as to form a negative capacitance; and an active layer of a semiconductor material, which layer is designed to form the channel of the transistor, and is arranged in direct contact with the ferroelectric layer. The NCFET transistor further comprises a channel that is arranged in the active layer, a source and a drain that are arranged in the active layer on either side of the channel, and a gate that is arranged on the channel and is insulated from the channel by a gate dielectric.

    HYBRID STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20240147864A1

    公开(公告)日:2024-05-02

    申请号:US18403485

    申请日:2024-01-03

    申请人: Soitec

    发明人: Didier Landru

    摘要: A hybrid structure and a method for manufacturing a hybrid structure comprising an effective layer of piezoelectric material having an effective thickness and disposed on a supporting substrate having a substrate thickness and a thermal expansion coefficient lower than that of the effective layer includes: a) a step of providing a bonded structure comprising a piezoelectric material donor substrate and the supporting substrate, b) a first step of thinning the donor substrate to form a thinned layer having an intermediate thickness and disposed on the supporting substrate, the assembly forming a thinned structure; c) a step of heat treating the thinned structure at an annealing temperature; and d) a second step, after step c), of thinning the thinned layer to form the effective layer. The method also comprises, prior to step b), a step a′) of determining a range of intermediate thicknesses that prevent the thinned structure from being damaged during step c).

    Surface elastic wave filter with resonant cavities

    公开(公告)号:US11962288B2

    公开(公告)日:2024-04-16

    申请号:US18248183

    申请日:2022-09-15

    申请人: Soitec

    IPC分类号: H03H9/64 H03H9/02

    CPC分类号: H03H9/643 H03H9/02653

    摘要: A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.

    SETUP METHOD FOR ADJUSTING THE TEMPERATURE CONDITIONS OF AN EPITAXY PROCESS

    公开(公告)号:US20240120240A1

    公开(公告)日:2024-04-11

    申请号:US18546210

    申请日:2022-01-28

    申请人: Soitec

    发明人: YoungPil Kim

    IPC分类号: H01L21/66 H01L21/02

    摘要: A setup method for an epitaxy process intended to form a useful layer on a receiving substrate, comprising:



    a) selecting a test substrate:

    having a thickness less than a usual thickness for a given substrate diameter, and/or
    having a low interstitial oxygen concentration, and/or
    comprising a SOI stack;


    b) fixing initial temperature conditions defining temperatures to be applied to areas of the substrate;
    c) forming a useful layer on the test substrate by applying the epitaxy process with the initial temperature conditions; then, measuring slip line defects;
    d) fixing new temperature conditions;
    e) forming a useful layer on a new test substrate of the same type, by applying the epitaxy process with the new temperature conditions; then, measuring slip line defects; and
    f) comparing the quantity of slip line defects measured on the test structures and choosing the temperature conditions generating the fewest slip line defects.

    Surface acoustic wave device on device on composite substrate

    公开(公告)号:US11936364B2

    公开(公告)日:2024-03-19

    申请号:US17043559

    申请日:2019-03-14

    申请人: Soitec

    摘要: A surface acoustic wave device comprising a base substrate, a piezoelectric layer and an electrode layer in between the piezoelectric layer and the base substrate, a comb electrode formed on the piezoelectric layer comprising a plurality of electrode means with a pitch p, defined asp=A, with A being the wavelength of the standing acoustic wave generated by applying opposite potentials to the electrode layer and comb electrode, wherein the piezoelectric layer comprises at least one region located in between the electrode means, in which at least one physical parameter is different compared to the region underneath the electrode means or fingers. A method of fabrication for such surface acoustic wave device is also disclosed. The physical parameter may be thickness, elasticity, doping concentration of Ti or number of protons obtained by proton exchange.