公开(公告)号：US20250056858A1

公开(公告)日：2025-02-13

申请号：US18720416

申请日：2022-11-16

Applicant: Soitec ,  Soitec Belgium

Inventor： Christelle Veytizou ,  lonut Radu ,  Joff Derluyn ,  Stefan Degroote

IPC: H01L29/20 ,  H01L21/762 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor structure includes a Silicon-On-Insulator substrate and an epitaxial III-N semiconductor layer stack on top of the Silicon-On-Insulator substrate. The Silicon-On-Insulator substrate has a silicon base layer, an intermediate layer on top of the base layer, and a n-type doped silicon top layer on top of the intermediate layer. The intermediate layer includes a trap-rich layer and a buried insulator on top of a trap-rich layer. The epitaxial III-N semiconductor layer stack, which is on top of the Silicon-On-Insulator substrate, includes a first active III-N layer and a second active III-N layer on top of the first active III-N layer. A two-dimensional Electron Gas is located between the first active III-N layer and the second active III-N layer.

公开(公告)号：US12270123B2

公开(公告)日：2025-04-08

申请号：US18247859

申请日：2021-10-04

Applicant: Soitec

Inventor： Eric Guiot

IPC: C30B25/02 ,  C30B25/20 ,  C30B29/40 ,  H01L21/762

Abstract: A method for producing a substrate for the epitaxial growth of a gallium-based III-N alloy layer comprises the following successive steps: —providing a donor substrate of single-crystal silicon carbide; —implanting ions in the donor substrate to form an embrittlement zone defining a thin film layer of single-crystal SiC; —bonding the donor substrate onto a first receiving substrate via a bonding layer; —detaching the donor substrate along the embrittlement zone to transfer the thin film of SiC onto the first receiving substrate; —epitaxially growing a layer of semi-insulating SiC having a thickness greater than 1 μm on the thin film of SiC; —bonding the layer of semi-insulating SiC onto a second receiving substrate having a high electrical resistivity; —removing at least a portion of the bonding layer to detach the first receiving substrate; and —removing the transferred thin film of single-crystal SiC, to expose the semi-insulating SiC layer.

公开(公告)号：US20250081561A1

公开(公告)日：2025-03-06

申请号：US18952033

申请日：2024-11-19

Applicant: Soitec ,  National University of Singapore

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Walter Schwarzenbach ,  Gong Xiao ,  Aaron Thean ,  Chen Sun ,  Haiwen Xu

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84 ,  H01L27/10 ,  H01L27/12 ,  H01L29/161 ,  H01L29/78

Abstract: A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.

公开(公告)号：US20250055442A1

公开(公告)日：2025-02-13

申请号：US18932048

申请日：2024-10-30

Applicant: Soitec

Inventor： Eric Michoulier ,  Sylvain Ballandras ,  Thierry LaRoche

IPC: H03H9/64 ,  H03H9/02

Abstract: A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.

公开(公告)号：US20250015122A1

公开(公告)日：2025-01-09

申请号：US18888578

申请日：2024-09-18

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

Abstract: A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

公开(公告)号：US12167694B2

公开(公告)日：2024-12-10

申请号：US17041355

申请日：2019-03-21

Applicant: Soitec

Inventor： Djamel Belhachemi ,  Thierry Barge

IPC: H10N30/057 ,  H03H3/02 ,  H10N30/073

Abstract: A method for transferring a piezoelectric layer onto a support substrate comprises: —providing a donor substrate including a heterostructure comprising a piezoelectric substrate bonded to a handling substrate, and a polymerized adhesive layer at the interface between the piezoelectric substrate and the handling substrate, —forming a weakened zone in the piezoelectric substrate, so as to delimit the piezoelectric layer to be transferred, —providing the support substrate, —forming a dielectric layer on a main face of the support substrate and/or of the piezoelectric substrate, —bonding the donor substrate to the support substrate, the dielectric layer being at the bonding interface, and—fracturing and separating the donor substrate along the weakened zone at a temperature below or equal to 300° C.

公开(公告)号：US20240387243A1

公开(公告)日：2024-11-21

申请号：US18688606

申请日：2022-10-19

Applicant: Soitec

Inventor： Youngpil Kim ,  Oleg Kononchuk ,  Chee Hoe Wong

IPC: H01L21/763 ,  H01L21/762 ,  H10N30/072

Abstract: A method for preparing a support substrate having a charge-trapping layer includes introducing a monocrystalline silicon base substrate into a chamber of deposition equipment and, without removing the base substrate from the chamber and while flushing the chamber with a carrier gas, performing the following successive steps: forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period; and forming a polycrystalline silicon charge-trapping layer directly on the dielectric layer by introducing a precursor gas containing silicon into the chamber over a second time period, subsequent to the first time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature strictly between 1010° C. and 1200° C.

公开(公告)号：US20240384432A1

公开(公告)日：2024-11-21

申请号：US18787009

申请日：2024-07-29

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: C30B25/18 ,  C30B23/02 ,  C30B29/36 ,  C30B29/40 ,  H01L21/02

Abstract: A structure comprises a carrier substrate, a plurality of tiles on the carrier substrate, and a plurality of monocrystalline layers of AlN material on the plurality of tiles. Each tile of the plurality of tiles comprises a monocrystalline seed layer of SiC-6H material. Each monocrystalline layer of AlN material of the plurality of monocrystalline layers of AlN material is disposed on a respective tile of the plurality of tiles. Also disclosed is substrate for epitaxial growth of monocrystalline layers of AlN material. The substrate comprises a carrier substrate and a plurality of tiles. Each tile of the plurality of tiles comprises a monocrystalline seed layer of SiC-6H material.

公开(公告)号：US20240379410A1

公开(公告)日：2024-11-14

申请号：US18784161

申请日：2024-07-25

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12

Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

公开(公告)号：US12143093B2

公开(公告)日：2024-11-12

申请号：US18352972

申请日：2023-07-14

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  A61B5/00 ,  A61B5/145 ,  A61B5/1459 ,  H03H3/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64 ,  H10N30/072 ,  H10N30/085 ,  H10N30/87 ,  H10N39/00

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.