公开(公告)号：US11012059B2

公开(公告)日：2021-05-18

申请号：US16856584

申请日：2020-04-23

Applicant: SONY CORPORATION

Inventor： Jacob Adams Wysocki

IPC: H03K5/135 ,  H04L7/033 ,  H03K3/017 ,  H03K5/134 ,  H03H7/32 ,  H03K19/017 ,  H03K5/00

Abstract: A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.

公开(公告)号：US10402166B2

公开(公告)日：2019-09-03

申请号：US15017330

申请日：2016-02-05

Applicant: SONY CORPORATION

Inventor： Jeremy Chatwin ,  Jacob Adams Wysocki

IPC: G06F7/504 ,  G06F7/509 ,  G06F7/523

Abstract: Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.