公开(公告)号：US20230118255A1

公开(公告)日：2023-04-20

申请号：US17771967

申请日：2021-12-11

Applicant: SOUTHEAST UNIVERSITY

Inventor： Fujin DENG ,  Yun ZHOU ,  Hanlu ZHANG ,  Chengkai LIU ,  Jianzhong ZHANG

IPC: G06F30/398 ,  H02J3/38

Abstract: The present invention discloses a method for modeling sequence impedance of a modular multilevel converter (MMC) under phase locked loop (PLL) coupling. The method includes the following steps: S1, establishing a circuit topology model; S2, establishing a PLL output characteristic model; S3, establishing a PI controller output control small signal model under a dq axis; S4, deducing a modulation small signal; and S5, calculating MMC port impedance. According to the method, a precise MMC port impedance model is established by analyzing a double mirror frequency coupling effect in the output of a modulation signal in a control link caused by a phase angle disturbance and comprehensively considering the combination of the multi-harmonic coupling effect of an MMC. On one hand, the proposed modeling method aims at a common MMC adopting current closed-loop control, in which a half-bridge sub-module is adopted, a circuit topological structure and a control structure are both more common, and a mathematical model is easy to establish. On the other hand, the physical significance of an impedance analysis method is clear, the modeling process is modular and is easy to understand and implement, and the inverter port impedance can be measured on site, so that the correctness of theoretical modeling can be conveniently verified.

公开(公告)号：US20240255584A1

公开(公告)日：2024-08-01

申请号：US18561221

申请日：2023-01-31

Applicant: SOUTHEAST UNIVERSITY

Inventor： Fujin DENG ,  Yufei CHEN ,  Chengkai LIU

IPC: G01R31/54

CPC classification number: G01R31/54

Abstract: The present invention discloses an isolation forest (IF)-based modular multilevel converter (MMC) open-circuit (OC) fault diagnosis method, including the following steps: sampling capacitor voltages of submodules (SM), constructing an isolation tree (IT) according to capacitor voltage data, and calculating a depth of each SM in the IT; and forming an IF based on the ITs, calculating average depths of the SMs in the IF, taking an SM with the minimum average depth as an output of the IT, and finally locating a faulty SM by an output buffer to realize accurate location of the faulty SM. Only capacitor voltages of SMs are involved, and no extra hardware resources are required. System parameters are not involved, construction of a system mathematical model and manual setting of an empirical threshold are not required, and the robustness is high. Faults are located using sparsity and difference of abnormal data based on unsupervised learning, mass data analysis and sample training are not required, and the method has the advantages of linear time complexity, small data volume, simple calculation process, low calculation cost, and the like.