公开(公告)号：US20230214567A1

公开(公告)日：2023-07-06

申请号：US18011443

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Jiahao WANG ,  Haiyang JIANG

IPC: G06F30/3315 ,  G06F30/337

CPC classification number: G06F30/3315 ,  G06F30/337 ,  G06F2119/12

Abstract: Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.

公开(公告)号：US20230195985A1

公开(公告)日：2023-06-22

申请号：US18014002

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng CAO ,  Haiyang JIANG ,  Jiahao WANG

IPC: G06F30/3312 ,  G06F30/3315

CPC classification number: G06F30/3312 ,  G06F30/3315 ,  G06F2119/12

Abstract: Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.