公开(公告)号：US11966678B2

公开(公告)日：2024-04-23

申请号：US17540774

申请日：2021-12-02

申请人： Synopsys, Inc.

发明人： Ruijing Shen ,  Li Ding

IPC分类号： G06F30/3312 ,  G06F30/31 ,  G06F30/3315 ,  G06F119/12

CPC分类号： G06F30/3312 ,  G06F30/31 ,  G06F30/3315 ,  G06F2119/12

摘要： A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

公开(公告)号：US11836433B2

公开(公告)日：2023-12-05

申请号：US17592404

申请日：2022-02-03

申请人： Synopsys, Inc.

发明人： John Edward Barth ,  Jeffrey C. Herbert ,  Matthew Christopher Lanahan

IPC分类号： G06F30/39 ,  G06F30/3312 ,  G06F30/3315

CPC分类号： G06F30/39 ,  G06F30/3312 ,  G06F30/3315

摘要： A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

公开(公告)号：US11797741B2

公开(公告)日：2023-10-24

申请号：US17700576

申请日：2022-03-22

申请人： FUJITSU LIMITED

发明人： Keisuke Nishida

IPC分类号： G06F30/3315 ,  G06F111/10 ,  G06F119/12

CPC分类号： G06F30/3315 ,  G06F2111/10 ,  G06F2119/12

摘要： A non-transitory computer-readable recording medium storing a timing library creation program of causing a computer to execute processing, the processing including: extracting, from a delay variation database that stores delay variation values of gates included in circuit design data, a delay variation value, out of the delay valuation values matching to characteristics which are characteristics of one of signal paths in the circuit design data and which include a threshold voltage, a drive force, and a number of gate stages of the signal path; calculating an extended delay variation coefficient based on the extracted delay variation value and the characteristics; and creating, based on a basic timing library in which the delay variation value is not reflected and the extended delay variation coefficient, an extended timing library in which the delay variation value is reflected.

公开(公告)号：US11775719B1

公开(公告)日：2023-10-03

申请号：US17713004

申请日：2022-04-04

申请人： Cadence Design Systems, Inc.

发明人： Igor Keller ,  Xiaopeng Dong ,  Sourabh Rajguru

IPC分类号： G06F30/30 ,  G06F30/3315 ,  G06F119/12

CPC分类号： G06F30/3315 ,  G06F2119/12

摘要： Various embodiments provide a charge model for a cell instance for delay calculation of a circuit design that includes the cell instance, where the charge model can be part of electronic design automation (EDA) and used in timing analysis of a circuit design that includes the cell instance. The charge model generated by an embodiment can predict a charge at an input of a cell instance for an arbitrary input voltage waveform and can address (e.g., reduce or negate) a time delay impact the Miller effect has on the cell instance.

公开(公告)号：US20230153502A1

公开(公告)日：2023-05-18

申请号：US16969474

申请日：2020-02-24

申请人： SOUTHEAST UNIVERSITY

发明人： Peng CAO ,  Tai YANG ,  Jingjing GUO

IPC分类号： G06F30/3315 ,  G06F30/3312

CPC分类号： G06F30/3315 ,  G06F30/3312 ,  G06F2119/12

摘要： It discloses a statistical timing analysis method of an integrated circuit under an advanced process and a low voltage. By simulating the fluctuation of process parameters of the integrated circuit under the advanced process, a statistical circuit timing model is built based on the relationship between the delay of the integrated circuit under the low voltage and the process parameters, and the maximum delay and the minimum delay under timing fluctuation of the integrated circuit are analyzed.

公开(公告)号：US12093634B2

公开(公告)日：2024-09-17

申请号：US18567044

申请日：2023-01-03

申请人： SOUTHEAST UNIVERSITY

发明人： Peng Cao ,  Xu Cheng ,  Tai Yang

IPC分类号： G06F30/398 ,  G06F30/27 ,  G06F30/33 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/392 ,  G06F30/3953

CPC分类号： G06F30/398 ,  G06F30/27 ,  G06F30/33 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/392 ,  G06F30/3953

摘要： A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

公开(公告)号：US20240152677A1

公开(公告)日：2024-05-09

申请号：US18402744

申请日：2024-01-03

申请人： SHENZHEN PANGO MICROSYSTEMS CO., LTD.

发明人： BO DENG ,  BIAO KONG ,  MIN ZHANG

IPC分类号： G06F30/343 ,  G06F30/327 ,  G06F30/3315 ,  G06F30/337 ,  G06F119/12

CPC分类号： G06F30/343 ,  G06F30/327 ,  G06F30/3315 ,  G06F30/337 ,  G06F2119/12

摘要： Provided are a method for optimizing a circuit structure based on an FPGA carry chain, a computer device and a non-transitory computer-readable storage medium, in which logic synthesis is performed, by a logic synthesis tool, on a target logic operation, and a synthesis netlist is obtained through the logic synthesis; a critical path is obtained in the synthesis netlist; and in response to the number of actual inputs of a look-up table in the critical path being not greater than a preset threshold, and at least one of elements adjacent to two ends of a reference path in the critical path being a carry chain, the look-up table in the critical path is converted into a carry chain, where the reference path includes the look-up table, and only one look-up table or multiple adjacent look-up tables compose the reference path.

公开(公告)号：US20240126966A1

公开(公告)日：2024-04-18

申请号：US18277147

申请日：2021-03-12

申请人： Siemens Industry Software Inc.

发明人： James Cooper

IPC分类号： G06F30/3308 ,  G06F30/3315

CPC分类号： G06F30/3308 ,  G06F30/3315 ,  G06F2119/12

摘要： A computing system implementing a design characterization tool can sample a distribution of values describing manufacturing variation for an integrated circuit described by a circuit design. The design characterization tool can utilize a set of the samples to generate a surrogate model of the circuit design, and can order another set of the samples based on predicted outputs of the surrogate model. The design characterization tool can simulate the surrogate model or the circuit design utilizing the ordered samples, and stop the simulations prior to all of the samples from the distribution having been utilized in the simulations. The design characterization tool can utilize a confidence interval stopping condition or a drought stopping condition to determine when to stop the simulations. The design characterization tool can utilize results of the simulations to characterize operational variation of the circuit design to the manufacturing variation described in the distribution of the values.

公开(公告)号：US11829693B2

公开(公告)日：2023-11-28

申请号：US18011443

申请日：2022-03-09

申请人： SOUTHEAST UNIVERSITY

发明人： Peng Cao ,  Jiahao Wang ,  Haiyang Jiang

IPC分类号： G06F30/3315 ,  G06F30/337 ,  G06F119/12

CPC分类号： G06F30/3315 ,  G06F30/337 ,  G06F2119/12

摘要： Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.

公开(公告)号：US20230222277A1

公开(公告)日：2023-07-13

申请号：US18150767

申请日：2023-01-05

申请人： REALTEK SEMICONDUCTOR CORP.

发明人： YING-CHIEH CHEN ,  MEI-LI YU ,  YU-LAN LO

IPC分类号： G06F30/3315

CPC分类号： G06F30/3315 ,  G06F2119/12

摘要： A margin correction method and a margin correction system for static timing analysis are provided. The margin calibration method includes: measuring dies on a to-be-tested chip with a target circuit to obtain performance data records; obtaining simulation data records for simulating performances of the dies; executing a static timing analysis (STA) tool to obtain timing analysis results; statistically calculating a simulation process corner based on the timing analysis results; obtaining a measurement process corner based on the performance data records; establishing a statistical model that defines a margin as a difference between the measurement process corner and the simulation process corner; substituting the timing analysis results and the measurement process corner into the statistical model and execute a model fitting algorithm, for fitting the statistical model to a target model to obtain the margin; and obtaining calibrated timing analysis results.