公开(公告)号：US11651766B2

公开(公告)日：2023-05-16

申请号：US17181908

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei Shan ,  Lixuan Zhu ,  Jun Yang ,  Longxing Shi

IPC: G10L15/02 ,  G06F17/14 ,  G10L25/24

CPC classification number: G10L15/02 ,  G06F17/142 ,  G10L25/24

Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

公开(公告)号：US11715456B2

公开(公告)日：2023-08-01

申请号：US17112246

申请日：2020-12-04

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei Shan ,  Lixuan Zhu

IPC: G06F17/14 ,  G10L15/02 ,  G10L25/27 ,  G10L25/45

CPC classification number: G10L15/02 ,  G06F17/141 ,  G10L25/27 ,  G10L25/45

Abstract: It discloses a serial FFT-based low-power MFCC speech feature extraction circuit, and belongs to the technical field of calculation, reckoning or counting. The circuit is oriented toward the field of intelligence, and is adapted to a hardware circuit design by optimizing an MFCC algorithm, and a serial FFT algorithm and an approximation operation on a multiplication are fully used, thereby greatly reducing a circuit area and power. The entire circuit includes a preprocessing module, a framing and windowing module, an FFT module, a Mel filtration module, and a logarithm and DCT module. The improved FFT algorithm uses a serial pipeline manner to process data, and a time of an audio frame is effectively utilized, thereby reducing a storage area and operation frequency of the circuit under the condition of meeting an output requirement.