METHOD FOR ATTACHING A HEAT SPREADER TO A SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLIES

    公开(公告)号:US20250125158A1

    公开(公告)日:2025-04-17

    申请号:US18914058

    申请日:2024-10-12

    Abstract: A method for attaching a heat spreader to a semiconductor package is provided. The method comprises: providing a semiconductor package, wherein the semiconductor package comprises a package substrate, a semiconductor component mounted on the package substrate and a mold cap formed on the package substrate and encapsulating the semiconductor component, and wherein the mold cap comprises a laser-activatable mold compound; removing a portion of a thickness of the mold cap above the semiconductor component by laser ablation to form a cavity in the mold cap and transform the laser-activatable mold compound at an inner surface of the cavity to a conductive layer; dispensing a thermal interface material (TIM) in the cavity to form on the conductive layer a TIM layer that protrudes from the mold cap; and attaching the heater spreader to the semiconductor package at least through the TIM layer.

    SEMICONDUCTOR PACAKGE AND METHOD FOR FORMING THE SAME

    公开(公告)号:US20250054925A1

    公开(公告)日:2025-02-13

    申请号:US18749657

    申请日:2024-06-21

    Abstract: A semiconductor package is provided, comprising: a package substrate; a first plurality of semiconductor dice disposed on a front side of the package substrate; an embedded sub-package disposed on a back side of the package substrate, comprising: a sub-package substrate, wherein a front side of the sub-package substrate is attached to the back side of the package substrate; an interconnection layer attached to a back side of the sub-package substrate, comprising a second plurality of vertical interconnection portions and at least one horizontal interconnection portion; and a second plurality of semiconductor dice disposed on the back side of the sub-package substrate through the interconnection layer; and a first plurality of vertical interconnection portions disposed on the back side of the package substrate; and solder bumps attached to the first plurality of vertical interconnection portions.

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