公开(公告)号：US20200335358A1

公开(公告)日：2020-10-22

申请号：US16918643

申请日：2020-07-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

公开(公告)号：US20170263470A1

公开(公告)日：2017-09-14

申请号：US15605010

申请日：2017-05-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

公开(公告)号：US11488838B2

公开(公告)日：2022-11-01

申请号：US16918643

申请日：2020-07-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

公开(公告)号：US10741416B2

公开(公告)日：2020-08-11

申请号：US15605010

申请日：2017-05-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.