公开(公告)号：US20200081476A1

公开(公告)日：2020-03-12

申请号：US16127771

申请日：2018-09-11

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Guenole LALLEMENT ,  Fady ABOUZEID

IPC: G05F3/20 ,  H03K19/0948 ,  H03K19/00 ,  G06F17/50 ,  H01L27/092 ,  H01L29/78

Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.