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公开(公告)号：US20230163754A1
公开(公告)日：2023-05-25
申请号：US18056153
申请日：2022-11-16
Inventor： Ugo MUREDDU , Gilles PELISSIER , Guillaume REYMOND
CPC classification number: H03K5/133 , H03K5/1565 , G11C8/18
Abstract: A wobulated signal generator includes a chain of delay elements and control circuitry. The chain of delay elements includes first delay elements, second delay elements, and third delay elements. The control circuitry, in operation, enables a number of the first delay elements, disables a number of the third delay elements, and enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at an output of the wobulated signal generator. The control circuitry monitors an average frequency of the digitally wobulated signal, and selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.
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公开(公告)号：US20210391977A1
公开(公告)日：2021-12-16
申请号：US17347369
申请日：2021-06-14
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Guillaume REYMOND , Thomas SARNO
IPC: H04L9/06
Abstract: A cryptographic device includes hardware data processing circuitry and software data processing circuitry coupled to the hardware data processing circuitry. The device, in operation, executes a plurality of rounds of a symmetrical data cipher algorithm and protects the execution of the plurality of rounds of the symmetrical data cipher algorithm. The protecting includes executing data masking and unmasking operations using the hardware data processing circuitry, executing linear operations applied to data using the software data processing circuitry, executing linear operations applied to masks using the hardware data processing circuitry, and executing non-linear operations applied to data using one of the hardware data processing circuitry or the software data processing circuitry.
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