公开(公告)号：US20240232342A9

公开(公告)日：2024-07-11

申请号：US18487697

申请日：2023-10-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thomas SARNO

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.

公开(公告)号：US20210391977A1

公开(公告)日：2021-12-16

申请号：US17347369

申请日：2021-06-14

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Guillaume REYMOND ,  Thomas SARNO

IPC: H04L9/06

Abstract: A cryptographic device includes hardware data processing circuitry and software data processing circuitry coupled to the hardware data processing circuitry. The device, in operation, executes a plurality of rounds of a symmetrical data cipher algorithm and protects the execution of the plurality of rounds of the symmetrical data cipher algorithm. The protecting includes executing data masking and unmasking operations using the hardware data processing circuitry, executing linear operations applied to data using the software data processing circuitry, executing linear operations applied to masks using the hardware data processing circuitry, and executing non-linear operations applied to data using one of the hardware data processing circuitry or the software data processing circuitry.

公开(公告)号：US20240134973A1

公开(公告)日：2024-04-25

申请号：US18487697

申请日：2023-10-15

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thomas SARNO

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.

公开(公告)号：US20230111089A1

公开(公告)日：2023-04-13

申请号：US17981191

申请日：2022-11-04

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thomas SARNO

IPC: G06F7/76 ,  G06F7/523 ,  G06F7/498

Abstract: A device includes a memory, which, in operation, stores one or more look-up tables, and cryptographic circuitry coupled to the memory. The cryptographic circuitry, in operation, multiplies first data masked with a first mask by second data masked with a second mask, and protects the first data and the second data during the multiplying. The multiplying and protecting includes remasking the first data with a third mask, remasking the second data with a fourth mask, executing one or more compensation operations using one or more of the one or more look-up tables, and generating third data masked with a fifth mask. The fifth mask is independent of the first, second, third, and fourth masks. The third data corresponds to the first data multiplied by the second data.