公开(公告)号：US09147453B2

公开(公告)日：2015-09-29

申请号：US14532174

申请日：2014-11-04

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

IPC: H05B1/02 ,  G11C7/22 ,  G11C7/06 ,  G11C7/08 ,  G11C29/12 ,  G11C29/14 ,  G11C29/50

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。