DETECTION CIRCUIT FOR AN ACTIVE DISCHARGE CIRCUIT OF AN X-CAPACITOR, RELATED ACTIVE DISCHARGE CIRCUIT, INTEGRATED CIRCUIT AND METHOD
    3.
    发明申请
    DETECTION CIRCUIT FOR AN ACTIVE DISCHARGE CIRCUIT OF AN X-CAPACITOR, RELATED ACTIVE DISCHARGE CIRCUIT, INTEGRATED CIRCUIT AND METHOD 审中-公开
    用于X电容器的有源放电电路的检测电路,相关的主动放电电路,集成电路和方法

    公开(公告)号:US20160124029A1

    公开(公告)日:2016-05-05

    申请号:US14838125

    申请日:2015-08-27

    Abstract: An active discharge circuit discharges an X. The detection circuit includes a sensor circuit that generates a sensor signal indicative of an AC oscillation voltage at the X capacitor. The detection circuit also includes a processing unit that generates the reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

    Abstract translation: 有源放电电路对X放电。检测电路包括传感器电路,其生成表示X电容器处的交流振荡电压的传感器信号。 检测电路还包括根据比较信号产生复位信号的处理单元。 比较器电路通过将传感器信号与阈值进行比较来生成比较信号。 当定时器电路通过复位信号复位时,定时器电路将放电使能信号设置为第一逻辑电平。 定时器电路确定自上次复位以来经过的时间,并测试经过的时间是否超过给定的超时值。 如果经过的时间超过给定的超时值,则定时器电路将放电使能信号设置为第二逻辑电平。 动态阈值发生器电路根据传感器信号改变比较器电路的阈值。

    QUALITY FACTOR ESTIMATION OF AN INDUCTIVE ELEMENT

    公开(公告)号:US20220069627A1

    公开(公告)日:2022-03-03

    申请号:US17461305

    申请日:2021-08-30

    Abstract: The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.

    Quality factor estimation of an inductive element

    公开(公告)号:US12160117B2

    公开(公告)日:2024-12-03

    申请号:US18154394

    申请日:2023-01-13

    Abstract: The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.

    Quality factor estimation of an inductive element

    公开(公告)号:US11588353B2

    公开(公告)日:2023-02-21

    申请号:US17461305

    申请日:2021-08-30

    Abstract: The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.

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