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公开(公告)号：US20190386816A1
公开(公告)日：2019-12-19
申请号：US16433847
申请日：2019-06-06
Applicant: STMicroelectronics S.r.l.
Inventor： Rosalino Critelli , Giuseppe Guarnaccia
Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.
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Patent Agency Ranking
公开(公告)号：US12174973B2
公开(公告)日：2024-12-24
申请号：US17737570
申请日：2022-05-05
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Rosalino Critelli
Abstract: A master device issues memory burst transaction requests via an interconnection bus to fetch data from a slave device. A cipher engine is coupled to the interconnection bus and decrypts the fetched data to produce plaintext data for the master device. The cipher engine selectively operates according to a stream cipher operation mode, or a block cipher operation mode. The cipher engine is configured to stall a read data channel of the interconnection bus between the slave device and the master device in response to the cipher engine switching from the block cipher operation mode to the stream cipher operation mode. The read data channel is reactivated in response to a last beat of a read burst of the plaintext data produced by the cryptographic engine.
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公开(公告)号：US11281807B2
公开(公告)日：2022-03-22
申请号：US16403275
申请日：2019-05-03
Inventor： Rosalino Critelli , Giuseppe Guarnaccia , Delphine Le-Goascoz , Nicolas Anquet
Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.
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公开(公告)号：US20190354726A1
公开(公告)日：2019-11-21
申请号：US16403275
申请日：2019-05-03
Inventor： Rosalino Critelli , Giuseppe Guarnaccia , Delphine Le-Goascoz , Nicolas Anquet
Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.
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公开(公告)号：US11456857B2
公开(公告)日：2022-09-27
申请号：US16433847
申请日：2019-06-06
Applicant: STMicroelectronics S.r.l.
Inventor： Rosalino Critelli , Giuseppe Guarnaccia
Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.
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公开(公告)号：US11042655B2
公开(公告)日：2021-06-22
申请号：US16296009
申请日：2019-03-07
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Giuseppe Guarnaccia , Rosalino Critelli
Abstract: A method for data decryption comprises receiving, over an AXI bus operating in burst mode, data access requests for data units stored in a memory, subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory, retrieving the respective sets of data units over the AXI bus, and applying Advanced Encryption Standard, AES, processing to the requests for encrypted data units by calculating decryption masks for the encrypted data units and applying the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.
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