LOW DROP OUT VOLTAGE REGULATOR AND RELATED METHOD OF GENERATING A REGULATED VOLTAGE
    1.
    发明申请
    LOW DROP OUT VOLTAGE REGULATOR AND RELATED METHOD OF GENERATING A REGULATED VOLTAGE 有权
    低压降稳压器及相关方法生成调节电压

    公开(公告)号:US20140312867A1

    公开(公告)日:2014-10-23

    申请号:US14097796

    申请日:2013-12-05

    CPC classification number: G05F1/56 G05F1/565

    Abstract: A low drop out voltage regulator includes an operational transconductance amplifier configured to be supplied with a supply voltage of the regulator, receive as inputs a reference voltage and a feedback voltage, and generate an intermediate current based upon a difference between the reference voltage and the feedback voltage. A current-to-voltage amplification stage is configured to be supplied with a boosted voltage greater than the supply voltage from a high voltage line, receive as input the intermediate current, and generate a driving voltage that is changed based upon the intermediate current. A pass transistor is controlled with the driving voltage to keep constant on a second conduction terminal thereof a regulated output voltage. A feedback network generates the feedback voltage based on the regulated output voltage.

    Abstract translation: 低压差稳压器包括:运算跨导放大器,被配置为提供调节器的电源电压,接收参考电压和反馈电压作为输入,并且基于参考电压和反馈之间的差产生中间电流 电压。 电流 - 电压放大级被配置为被提供大于来自高压线的电源电压的升压电压,作为输入接收中间电流,并且产生基于中间电流而改变的驱动电压。 通过驱动电压来控制传输晶体管,以在其第二导通端子上保持恒定的稳定的输出电压。 反馈网络基于稳压输出电压产生反馈电压。

    TRANSCEIVER SUITABLE FOR IO-LINK DEVICES AND RELATED IO-LINK DEVICE
    3.
    发明申请
    TRANSCEIVER SUITABLE FOR IO-LINK DEVICES AND RELATED IO-LINK DEVICE 有权
    适用于IO链接设备和相关IO链接设备的收发器

    公开(公告)号:US20150003503A1

    公开(公告)日:2015-01-01

    申请号:US14307098

    申请日:2014-06-17

    Abstract: A transceiver is connectable to a cable with at least three wires. The transceiver may include a controlled output stage including a high-side leg, having two P-type transistors coupled in series and having a common current terminal, coupled between an output pin and a positive supply pin. The P-type transistors have body regions coupled to the common current terminal of the high-side leg. A low-side leg, includes two N-type transistors coupled in series and having a common current terminal, coupled between the output pin and a negative supply pin. The N-type transistors have body regions coupled to the common current terminal of the low-side leg. The protection circuit also includes a voltage clamper coupled between the common current terminals.

    Abstract translation: 收发器可连接至具有至少三根电线的电缆。 收发器可以包括受控的输出级,包括高侧支路,具有耦合在输出引脚和正电源引脚之间的具有串联耦合并具有公共电流端子的两个P型晶体管。 P型晶体管具有耦合到高侧支腿的公共电流端子的主体区域。 低侧支腿包括串联耦合并具有公共电流端子的两个N型晶体管,耦合在输出引脚和负电源引脚之间。 N型晶体管具有耦合到低侧支腿的公共电流端子的主体区域。 保护电路还包括耦合在公共电流端子之间的电压钳位器。

    VOLTAGE REGULATION CIRCUIT
    4.
    发明公开

    公开(公告)号:US20240329674A1

    公开(公告)日:2024-10-03

    申请号:US18611321

    申请日:2024-03-20

    CPC classification number: G05F1/462 G05F1/575 G05F3/262

    Abstract: The present disclosure is directed to a voltage regulation circuit receiving as input an input voltage, in particular a DC voltage supply, and outputting a regulated voltage. The voltage regulation circuit includes a voltage reference circuit configured to supply a reference voltage which is independent, in particular with respect to temperature variations. The voltage regulation circuit includes a first circuit branch and a second circuit branch in parallel coupled between the input voltage and ground. The first branch includes a current generator including a first depletion MOSFET transistor, which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between the input voltage and the voltage reference circuit. The voltage reference circuit includes a first enhancement MOSFET transistor, which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground by its source through a source resistor, on which a reference voltage, sum of the PTAT voltage drop on the source resistor and of the gate source voltage of the enhancement MOSFET transistor being formed. The first enhancement MOSFET transistor is arranged on the first branch and coupled by the drain to the first depletion MOSFET transistor in a control node. The control node is coupled to the gate of the first enhancement MOSFET transistor. The first depletion MOSFET transistor injects a PTAT current in the first branch determining a PTAT voltage drop on the source resistor. The second branch includes an output stage coupled between the voltage to regulate and an output node on which the regulated voltage is taken. The output stage includes a second depletion MOSFET transistor on which output is taken at the output node. A resistive voltage divider is coupled to the output node, outputting on a respective divider output node a divided output regulated voltage which is inputted as the process variable of a negative feedback loop which is also coupled to the reference voltage. The output of the negative feedback loop controls the gate of the second MOSFET transistor.

    DC-DC CONVERTER WITH GALVANIC ISOLATION AND CORRESPONDING METHOD OF CONTROL OF A DC-DC CONVERTER

    公开(公告)号:US20240291387A1

    公开(公告)日:2024-08-29

    申请号:US18437919

    申请日:2024-02-09

    CPC classification number: H02M3/33523 H02M1/0054 H02M3/01 H02M3/3384

    Abstract: Provided is a DC-DC converter with galvanic isolation comprising a resonant oscillator coupled to a primary winding of a galvanic isolation transformer. A rectifier is coupled to a secondary winding of the transformer to provide an output voltage. The DC-DC converter comprises a regulation loop configured to regulate an output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator as a function of a result of a signal indicative of the comparison between the output voltage and the reference voltage. The resonant oscillator is configured to operate at a frequency, in particular tuned at sub-resonant point, in particular sub-harmonic frequency, below a resonance frequency of the resonant oscillator which maximizes a quality factor of the resonant oscillator, in particular below a resonance frequency of a LC tank circuit comprised in the resonant oscillator which maximizes a quality factor of the LC tank circuit.

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